Low-test memory stack for non-volatile storage

• US 9,613,715 B2
• Filed: 03/09/2015
• Issued: 04/04/2017
• Est. Priority Date: 06/16/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Frayer, Jack Edward, Mohan, Vidyabhushan
• Primary Examiner(s): LE, TOAN K
• Application Number:
  US14/642,611
• Publication Number:
  US 20150364215A1
• Time in Patent Office: 757 Days
• Field of Search: 365201, 32475401, 714 25
• CPC Class Codes: G11C 16/00 Erasable programmable read-only memories G11C14/00 takes precedence
• CPC Class Codes: G11C 2029/0403 during or with feedback to manufacture
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: G11C 29/04 Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals
• CPC Class Codes: G11C 29/08 Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
• CPC Class Codes: G11C 29/10 Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The various embodiments described herein include systems, methods and/or devices used to package non-volatile memory. In one aspect, the method includes: (1) selecting, from a set of non-volatile memory die, a plurality of non-volatile memory die on which one or more tests have been deferred until after packaging, the selecting in accordance with wafer positions of the plurality of non-volatile memory die and statistical die performance information corresponding to the wafer positions; and (2) packaging the selected plurality of non-volatile memory die. In some embodiments, after said packaging, the method further includes performing a set of tests on the plurality of non-volatile memory die to identify respective units of memory within the plurality of non-volatile memory die that meet predefined validity criteria, wherein the set of tests performed include at least one of the deferred one or more tests.

Claims

1. A method for packaging non-volatile memory, comprising:

selecting, from a set of non-volatile memory die, a plurality of non-volatile memory die on which one or more tests have been deferred until after packaging, the selecting in accordance with wafer positions of the plurality of non-volatile memory die and statistical die performance information corresponding to the wafer positions; and

packaging the selected plurality of non-volatile memory die.

2. The method of claim 1, wherein the selecting includes:

in accordance with the statistical die performance information, selecting a number of die so as to over-provision the packaged non-volatile memory to guarantee, within a predefined statistical tolerance, at least a predefined amount of programmable/erasable memory in the packaged non-volatile memory.

3. The method of claim 1, further including:

after said packaging, performing a set of tests on the plurality of non-volatile memory die to identify respective units of memory within the plurality of non-volatile memory die that meet predefined validity criteria, wherein the set of tests performed include at least one of the deferred one or more tests.

4. The method of claim 3, wherein at least one test of the set of tests is performed by a host system under control of system application software.

5. The method of claim 1, wherein the one or more tests that have been deferred until after packaging include at least one predefined die-level test.

6. The method of claim 1, wherein the one or more tests that have been deferred until after packaging include at least one predefined sub-die-level test.

7. The method of claim 1, further including:

deferring, at least until the selected plurality of non-volatile memory die are packaged, performance of at least one of the following tests;

a wafer sort test, a known good die test, and a burn-in test.

8. The method of claim 1, further including:

forgoing performance of at least one of the following tests;

a wafer sort test, a memory component test, a known good die test, and a burn-in test.

9. The method of claim 1, further including:

after packaging the plurality of non-volatile memory die, determining an amount of programmable/erasable memory in the packaged non-volatile memory.

10. The method of claim 1, further including:

after packaging the plurality of non-volatile memory die, during initialization of the packaged non-volatile memory, performing an initialization procedure that includes;

determining a validity state of one or more units of memory of the plurality of non-volatile memory die, the validity state being one of a valid state or an invalid state; and

using physical-to-physical address remapping to redirect a read/write request addressed to a respective unit of memory having an invalid state to a unit of memory having a valid state.

11. The method of claim 10, wherein determining the validity state of the one or more units of memory includes:

determining a validity metric of the one or more units of memory; and

comparing the validity metric to a predefined threshold to determine the validity state of the one or more units of memory.

12. The method of claim 11, wherein the validity metric is a bit error rate (BER) of the one or more units of memory during initialization.

13. The method of claim 11, further including:

writing to the plurality of non-volatile memory die in accordance with a wear leveling algorithm that accounts for the validity metric determined during initialization.

14. The method of claim 1, wherein the set of non-volatile memory die comprises flash memory.

15. The method of claim 1, wherein a median number of program/erase (P/E) cycles performed on units of memory of the plurality of non-volatile memory die prior to the packaging is less than fifty P/E cycles.

16. A storage system, comprising:

an interface for operatively coupling the storage system with a host system; and

a plurality of non-volatile memory die selected and packaged in accordance with the method of claim 1.