Multi-chip non-volatile semiconductor memory package including heater and sensor elements

• US 9,613,719 B1
• Filed: 03/05/2015
• Issued: 04/04/2017
• Est. Priority Date: 02/17/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Darryl G. Walker
• Inventors: Walker, Darryl G.
• Primary Examiner(s): ZARROLI, MICHAEL C
• Application Number:
  US14/639,270
• Time in Patent Office: 761 Days
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 29/70 Masking faults in memories by using spares or by reconfiguring
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 22/10 Measuring as part of the manufacturing process burn-in G01R31/2855
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/345 Arrangements for heating thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H05B 3/146 : Conductive polymers, e.g. polyethylene, thermoplastics
• CPC Class Codes: H05B 3/148 : Silicon, e.g. silicon carbide, magnesium silicide, heating transistors or diodes
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 69/00 : Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method of healing a plurality of non-volatile semiconductor memory devices on a multi-chip package is disclosed. The multi-chip package can be heated to a temperature range having a temperature range upper limit value and a temperature range lower limit value. The temperature of the multi-chip package can be kept essentially within the temperature range for a predetermined time period by monitoring a thermal sensing element with a sensing circuit outside of the multi-chip package. The thermal sensing element may be located near the components with the lowest failure temperature to ensure the multi-chip package is not damaged during the healing process.

Claims

1. A method of healing a non-volatile memory system, comprising the steps of:

heating a package including at least one non-volatile semiconductor memory device to a temperature within a temperature range, the temperature range having a temperature range upper value and a temperature range lower value;

maintaining the temperature of the package essentially within the temperature range for a predetermined time period; and

generating a temperature upper range limit detect signal, the temperature upper range limit detect signal having

a first upper range logic level when a thermal sensing element has a temperature below the temperature range upper value, and

a second upper range logic level when the thermal sensing element has a temperature above the temperature range lower value;

wherein

the package includes the thermal sensing element.

2. The method of claim 1, further including the step of:

generating a temperature lower range limit detect signal, the temperature lower range limit detect signal having

a first lower range logic level when the thermal sensing element has a temperature below the temperature range lower value and

a second lower range logic level when the thermal sensing element has a temperature above the temperature range lower value.

3. The method of claim 2, wherein:

the step of maintaining includes preventing current from flowing through a heater element in response to the temperature range upper limit detect signal having the second upper range logic level wherein the package includes the heating element.

4. The method of claim 3, wherein:

the step of maintaining includes allowing current to flow through the heater element in response to the lower range limit detect signal having the first temperature range lower logic level.

5. The method of claim 4, wherein:

the package includes the at least one non-volatile semiconductor memory device sandwiched between the heater element and the thermal sensing element.

6. The method of claim 1, wherein:

the package includes the thermal sensing element between the at least one non-volatile semiconductor memory device and a plurality of solder connections.

7. The method of claim 1, wherein:

the at least one non-volatile semiconductor memory device is a plurality of non-volatile semiconductor memory devices stacked within the package.

8. The method of claim 1, wherein:

the temperature range upper value is less than or equal to 10°

C. greater than the temperature range lower value.

9. The method of claim 1, wherein:

the package includes solder connections and the temperature range upper value is less than the melting point of the solder connections.

10. A method of healing a non-volatile memory system, comprising the steps of:

heating a package including at least one non-volatile semiconductor memory device to a temperature within a temperature range, the temperature range having a temperature range upper value and a temperature range lower value;

maintaining the temperature of the package essentially within the temperature range for a predetermined time period; and

generating a temperature lower range limit detect signal, the temperature lower range limit detect signal having

a first lower range logic level when a thermal sensing element has a temperature below a temperature range lower value and

a second lower range logic level when the thermal sensing element has a temperature above the temperature range lower value.

11. The method of claim 10, further including the step of:

generating a temperature upper range limit detect signal having a first upper range logic level when a thermal sensing element has a temperature below the temperature range upper value and a second upper range logic level when the thermal sensing element has a temperature above the temperature range lower value wherein the package includes the thermal sensing element.

12. The method of claim 11, wherein:

the step of maintaining includes preventing current from flowing through a heater element in response to the temperature range upper limit detect signal having the second temperature range upper logic level.

13. The method of claim 12, wherein:

the step of maintaining includes allowing current to flow through the heater element in response to the temperature range lower limit detect signal having the first lower range logic level.

14. The method of claim 13, wherein:

the package includes the at least one non-volatile semiconductor memory device sandwiched between the heater element and the thermal sensing element.

15. The method of claim 10, wherein:

the package includes the thermal sensing element between the at least one non-volatile semiconductor memory device and a plurality of solder connections.

16. The method of claim 10, wherein:

the at least one non-volatile semiconductor memory device is a plurality of non-volatile semiconductor memory devices stacked within the package.

17. The method of claim 10, wherein:

the temperature range upper value is less than or equal to 10°

C. greater than the temperature range lower value.

18. The method of claim 10, wherein:

the package includes solder connections and the temperature range upper value is less than the melting point of the solder connections.