Low defect relaxed SiGe/strained Si structures on implant anneal buffer/strain relaxed buffer layers with epitaxial rare earth oxide interlayers and methods to fabricate same

• US 9,613,803 B2
• Filed: 04/30/2015
• Issued: 04/04/2017
• Est. Priority Date: 04/30/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Reznicek, Alexander
• Primary Examiner(s): Dickey, Thomas L
• Assistant Examiner(s): Yi, Changhyun
• Application Number:
  US14/700,568
• Publication Number:
  US 20160322220A1
• Time in Patent Office: 705 Days
• Field of Search: 438479
• CPC Class Codes: H01L 21/02192 the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium
• CPC Class Codes: H01L 21/02194 the material containing more than one metal element
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02483 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/02516 Crystal orientation
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02694 Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/32 the imperfections being within the semiconductor body
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method provides a substrate having a top surface; forming a first semiconductor layer on the top surface, the first semiconductor layer having a first unit cell geometry; epitaxially depositing a layer of a metal-containing oxide on the first semiconductor layer, the layer of metal-containing oxide having a second unit cell geometry that differs from the first unit cell geometry; ion implanting the first semiconductor layer through the layer of metal-containing oxide; annealing the ion implanted first semiconductor layer; and forming a second semiconductor layer on the layer of metal-containing oxide, the second semiconductor layer having the first unit cell geometry. The layer of metal-containing oxide functions to inhibit propagation of misfit dislocations from the first semiconductor layer into the second semiconductor layer. A structure formed by the method is also disclosed.

Claims

1. A method comprising:

providing a substrate having a top surface;

forming a first semiconductor layer on the top surface of the substrate, the first semiconductor layer having a first unit cell geometry;

epitaxially depositing a layer comprised of a metal-containing oxide on the first semiconductor layer, the layer of metal-containing oxide having a second unit cell geometry that differs from the first unit cell geometry;

ion implanting the first semiconductor layer through the layer comprised of a metal-containing oxide;

annealing the ion implanted first semiconductor layer; and

forming a second semiconductor layer on the layer comprised of a metal-containing oxide, the second semiconductor layer having the first unit cell geometry;

where the step of implanting forms dislocation nucleation centers in the first semiconductor layer, where the step of annealing forms misfit dislocations originating from the nucleation centers, and where the metal-containing oxide layer inhibits propagation of the misfit dislocations into the second semiconductor layer.

2. The method of claim 1, wherein the first semiconductor layer and the second semiconductor layer are both comprised of Si_1-xGe_x, and where the metal-containing oxide layer is comprised of a rare earth metal.

3. The method of claim 1, wherein the first semiconductor layer and the second semiconductor layer are both comprised of Si_1-xGe_x, and where the metal-containing oxide layer is comprised of at least one of cerium oxide (CeO₂), lanthanum oxide (La₂O₃), yttrium oxide (Y₂O₃), gadolinium oxide (Gd₂O₃), europium oxide (Eu₂O₃), terbium oxide (Tb₂O₃), a material ABO₃, where ‘

A’ and

‘

B’

may be any rare earth metal including lanthanum scandium oxide (LaScO₃) and lanthanum yttrium oxide (La_xY_1-x)₂O₃, samarium yttrium oxide (Sm_xY_1-x)₂O₃ lanthanum gadolinium oxide (La_xGd_1-x)₂O₃ and gadolinium europium oxide (Gd_xEu_1-x)₂O₃.

4. The method of claim 1, where the first semiconductor layer is formed as a strained layer comprised of Si_1-xGe_x, and where the step of annealing strain relaxes the first semiconductor layer.

5. The method of claim 1, where the first unit cell geometry exhibits a diamond lattice crystal structure, and where the second unit cell geometry exhibits is a cubic lattice crystal structure.

6. The method of claim 1, where the step of epitaxially depositing the layer comprised of the metal-containing oxide deposits the layer to have a thickness in a range of about 10 nm to about 100 nm, or a thickness in an range of about 20 nm to about 50 nm, or to have a thickness of about 30 nm.

7. The method of claim 1, where the second semiconductor layer is Si_1-xGe_x, and further comprising depositing a layer of strained silicon on a top surface of the second semiconductor layer.

8. The method of claim 1, where the first semiconductor layer is Si_1-xGe_x, and further comprising depositing a further layer of Si_1-xGe_x on a top surface of the second semiconductor layer, where the value of x in the further layer of Si_1-xGe_x concentration is greater than the value of x in the first semiconductor layer.