Area array semiconductor device package interconnect structure with optional package-to-package or flexible circuit to package connection

• US 9,613,841 B2
• Filed: 03/02/2012
• Issued: 04/04/2017
• Est. Priority Date: 06/02/2009
• Status: Active Grant

• Current Assignee: HSIO Technologies LLC
• Original Assignee: HSIO Technologies LLC
• Inventors: Rathburn, James
• Primary Examiner(s): Montalvo, Eva Y
• Assistant Examiner(s): GOODWIN, DAVID J
• Application Number:
  US13/410,943
• Publication Number:
  US 20120161317A1
• Time in Patent Office: 1,859 Days
• Field of Search: 438 14, 438 17, 438 15, 438 18, 257773, 257686, 257723
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/81005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81201 Compression bonding
• CPC Class Codes: H01L 2224/8138 Bonding interfaces outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/819 with the bump connector not providing any mechanical bonding
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01087 Francium [Fr]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components

Abstract

An area array integrated circuit (IC) package for an IC device. The IC package includes a first substrate with conductive traces electrically coupled to the IC device. An interconnect assembly having a first surface is mechanically coupled to the first substrate. The interconnect assembly includes a plurality of contact members electrically coupled to the conductive traces on the first substrate. A second substrate is mechanically coupled to a second surface of the interconnect assembly so that the first substrate, the interconnect assembly, and the second substrate substantially surround the IC device. The second substrate includes conductive traces that are electrically coupled to the contact members in the interconnect assembly.

Claims

1. A method of making an area array integrated circuit (IC) package for an IC device, the method comprising the steps of:

electrically coupling a first surface of the IC device to conductive traces on a first surface of a first substrate;

mechanically coupling a first surface of an interconnect assembly to the first surface of the first substrate;

locating contact members in openings formed in a second surface of the interconnect assembly, the contact members including elongated beams extending in the openings generally perpendicular to the second surface of the interconnect assembly;

electrically coupling the contact members located in the openings in the interconnect assembly to the conductive traces on the first surface of the first substrate;

positioning a second substrate opposite the IC device and the first surface of the first substrate, the interconnect assembly maintaining a separation between the first and second substrates that creates a recess and maintaining a separation between a second opposite surface of the IC device and the second substrate, the separation between the first and second substrates being greater than a separation between the first and second surfaces of the IC device, so the IC device is located in the recess and interposed between the first and second substrates;

inserting solder balls attached to, and electrically coupled with, conductive traces on a second substrate into the openings located along a second surface of the interconnect assembly so that the first substrate, the interconnect assembly, and the second substrate substantially surround the IC device; and

electrically coupling the solder balls on the second substrate to the contact members located in the openings in the interconnect assembly, comprising deflecting contact beams on the contact members outward to mechanically compressively couple with the solder balls.

2. The method of claim 1 wherein the second substrate comprises one of a PCB, a flexible circuit, a packaged IC device, or another IC package.

3. The method of claim 1 comprising the step of deflecting contact beams on the contact members outward to electrically couple with solder balls attached to, and electrically coupled with, the conductive traces on the first or second substrates.

4. The method of claim 1 comprising the steps of:

bonding electrically conductive contact tabs to a first surface of the interconnect assembly so that contact tips on the contact tabs extend into the openings in the interconnect assembly; and

inserting solder balls attached to, and electrically coupled with, the conductive traces on the first or second substrates into the openings to electrically couple with the contact tabs.

5. The method of claim 4 comprising the step of locating a plurality of conductive contact tabs that extend into the openings in a spaced configuration.

6. The method of claim 1 comprising forming the interconnect assembly as a layered structure wherein one of the layers comprise a circuitry plane selected from one of a ground plane, a power plane, an electrical connection to other circuit members, a dielectric layer, or a flexible circuit.

7. The method of claim 1 comprising the steps of:

printing at least one printed electrical device on the interconnect assembly; and

electrically coupling the electrical device with at least a one of the contact members.

8. The method of claim 1 comprising attaching the interconnect assembly to the first substrate using surface mount technology.