Semiconductor system, device and structure

• US 9,613,887 B2
• Filed: 03/23/2016
• Issued: 04/04/2017
• Est. Priority Date: 08/10/2012
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Sekar, Deepak, Or-Bach, Zvi, Cronquist, Brian
• Primary Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US15/079,017
• Publication Number:
  US 20160204085A1
• Time in Patent Office: 377 Days
• Field of Search: 257347, 257758, 257686, 257712
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between at least a portion of the plurality of first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second transistors, the second layer overlying the at least one metal layer; and at least one conductive structure constructed to provide power to a portion of the second transistors, where the provide power is controlled by at least one of the transistors.

Claims

1. An Integrated Circuit device, comprising:

a base wafer comprising single crystal, said base wafer comprising a plurality of first transistors;

at least one metal layer providing interconnection between at least a portion of said plurality of first transistors;

a second layer of less than 2 micron thickness, said second layer comprising a plurality of second transistors, said second layer overlying said at least one metal layer; and

at least one conductive structure constructed to provide power to a portion of said second transistors,

wherein said provide power is controlled by at least one of said transistors, and

wherein said at least one conductive structure provides a heat removal path between at least one of said second transistors and a top or bottom surface of said device.

2. An Integrated Circuit device, comprising:

a base wafer comprising single crystal, said base wafer comprising a plurality of first transistors;

at least one metal layer providing interconnection between at least a portion of said plurality of first transistors;

a second layer of less than 2 micron thickness, said second layer comprising a plurality of second transistors, said second layer overlying said at least one metal layer; and

at least one conductive structure constructed to provide power to a portion of said second transistors,

wherein said provide power is controlled by at least one of said transistors; and

a via through said second layer,

wherein said via is part of a heat removal structure of said device.

3. An Integrated Circuit device, comprising:

a base wafer comprising single crystal, said base wafer comprising a plurality of first transistors;

at least one metal layer providing interconnection between at least a portion of said plurality of first transistors;

a second layer of less than 2 micron thickness, said second layer comprising a plurality of second transistors, said second layer overlying said at least one metal layer; and

at least one conductive structure constructed to provide power to a portion of said second transistors,

wherein said provide power is controlled by at least one of said transistors; and

a heat-spreader layer disposed between said first layer and said second layer.

4. An Integrated Circuit device, comprising:

a base wafer comprising single crystal, said base wafer comprising a plurality of first transistors;

at least one metal layer providing interconnection between at least a portion of said plurality of first transistors;

a second layer of less than 2 micron thickness, said second layer comprising a plurality of second transistors, said second layer overlying said at least one metal layer; and

at least one conductive structure constructed to provide power to a portion of said second transistors,

wherein said provide power is controlled by at least one of said transistors; and

at least one pad designed to connect said at least one conductive structure to external devices.

5. An Integrated Circuit device, comprising:

a base wafer comprising single crystal, said base wafer comprising a plurality of first transistors;

at least one metal layer providing interconnection between at least a portion of said plurality of first transistors;

a second layer of less than 2 micron thickness, said second layer comprising a plurality of second transistors, said second layer overlying said at least one metal layer; and

at least one conductive structure constructed to provide power to a portion of said second transistors,

wherein said provide power is controlled by at least one of said transistors, and

wherein said at least one conductive structure is designed by an engineering design automation tool in consideration of its heat removal capabilities.

6. An Integrated Circuit device, comprising:

a base wafer comprising single crystal, said base wafer comprising a plurality of first transistors;

at least one metal layer providing interconnection between at least a portion of said plurality of first transistors;

a second layer of less than 2 micron thickness, said second layer comprising a plurality of second transistors, said second layer overlying said at least one metal layer; and

at least one conductive structure constructed to provide power to a portion of said second transistors,

wherein said provide power is controlled by at least one of said transistors, and

wherein said at least one conductive structure comprises at least two layers, and

wherein said at least two layers comprise a global power grid and a local power grid.

7. An Integrated Circuit device, comprising:

a base wafer comprising single crystal, said base wafer comprising a plurality of first transistors;

at least one metal layer providing interconnection between said plurality of first transistors;

a first wire structure constructed to provide power to a portion of said first transistors;

a second layer of less than 2 micron thickness, said second layer comprising a plurality of second transistors, said second layer overlying said at least one metal layer; and

a second wire structure constructed to provide power to a portion of said second transistors,

wherein said second wire structure has a current carrying capacity substantially higher than said first wire structure.

8. The device according to claim 7,

wherein said second wire structure provides a heat removal path between at least one of said second transistors and a top or bottom surface of said device.

9. The device according to claim 7, further comprising:

a via through said second layer,

wherein said via is part of a heat removal structure of said device.

10. The device according to claim 7, further comprising:

a heat-spreader layer disposed between said first layer and said second layer.

11. The device according to claim 7, further comprising:

at least one pad designed to connect said second wire structure to external devices.

12. The device according to claim 7,

wherein said second wire structure is designed by an engineering design automation tool in consideration of its heat removal capabilities.

13. The device according to claim 7,

wherein said second wire structure comprises at least two layers, and

wherein said at least two layers comprise a global power grid and a local power grid.

14. An Integrated Circuit device, comprising:

a base wafer comprising single crystal, said base wafer comprising a plurality of first transistors;

at least one metal layer providing interconnection between said plurality of first transistors;

a second layer of less than 2 micron thickness, said second layer comprising a plurality of second transistors, said second layer overlying said at least one metal layer; and

a conductive structure constructed to provide power to a portion of said second transistors,

wherein said conductive structure comprises at least two layers, and

wherein said two layers comprise a global power grid and a local power grid.

15. The device according to claim 14,

wherein said conductive structure provides a heat removal path between at least one of said second transistors and a top or bottom surface of said device.

16. The device according to claim 14, further comprising:

a via through said second layer,

wherein said via is part of a heat removal structure of said device.

17. The device according to claim 14, further comprising:

a heat-spreader layer disposed between said first layer and said second layer.

18. The device according to claim 14, further comprising:

at least one pad designed to connect said conductive structure to external devices.

19. The device according to claim 14,

wherein said conductive structure is designed by an engineering design automation tool in consideration of its heat removal capabilities.