Electronic packages for flip chip devices

• US 9,613,891 B2
• Filed: 12/14/2015
• Issued: 04/04/2017
• Est. Priority Date: 02/24/2015
• Status: Active Grant

• Current Assignee: Navitas Semiconductor Limited (Navitas Semiconductor Corp.)
• Original Assignee: Navitas Semiconductor, Inc.
• Inventors: Kinzer, Daniel M.
• Primary Examiner(s): Naraghi, Ali
• Application Number:
  US14/968,688
• Publication Number:
  US 20160247748A1
• Time in Patent Office: 477 Days
• Field of Search: None
• CPC Class Codes: H01L 21/4825 Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
• CPC Class Codes: H01L 21/4828 Etching etching for cleaning without patterning H01L21/4835
• CPC Class Codes: H01L 21/4842 Mechanical treatment, e.g. punching, cutting, deforming, cold welding
• CPC Class Codes: H01L 21/4882 Assembly of heatsink parts
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/371 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/37124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/37147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/37599 Material
• CPC Class Codes: H01L 2224/40245 the item being metallic
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73255 Bump and strap connectors
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/4951 Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
• CPC Class Codes: H01L 23/4952 : the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49524 : the additional leads being a tape carrier or flat leads
• CPC Class Codes: H01L 23/49548 : Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49562 : for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49568 : specifically adapted to facilitate heat dissipation
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/49586 : Insulating layers on lead frames
• CPC Class Codes: H01L 29/2003 : Nitride compounds
• CPC Class Codes: H01L 29/41758 : for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/7787 : with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/18161 : of a flip chip

Abstract

Electronic packages are formed from a generally planar leadframe having a plurality of leads coupled to a GaN-based semiconductor device, and are encased in an encapsulant. The plurality of leads are interdigitated and are at different voltage potentials.

Claims

1. An electronic package comprising:

a leadframe having a thickness extending from a top surface of the leadframe to a bottom surface of the leadframe and comprising;

a first terminal having a plurality of first terminal fingers extending therefrom and a second terminal having a plurality of second terminal fingers extending therefrom wherein the plurality of first terminal fingers are interdigitated with the plurality of second terminal fingers;

a third terminal having at least one third terminal finger;

wherein the first terminal, the second terminal and the third terminal have a first thickness extending from the top surface of the leadframe to the bottom surface of the leadframe; and

wherein the first terminal fingers, the second terminal fingers and the at least one third terminal finger have a second thickness extending from the top surface of the leadframe to an intermediate plane that is located between the top surface and the bottom surface of the leadframe;

a GaN-based die electrically coupled to the top surface of the leadframe, and including a source pad having a plurality of source fingers and a drain pad having a plurality of drain fingers wherein the plurality of source fingers are interdigitated with the plurality of drain fingers, and a gate pad;

a plurality of interconnects disposed between the GaN-based die and the top surface of the leadframe and configured to provide electrical continuity between the plurality of first terminal fingers and the plurality of drain fingers, between the plurality of second terminal fingers and the plurality of source fingers and between the third terminal finger and the at least one gate pad, respectively;

a first encapsulant adhered to the leadframe such that it encapsulates the GaN-based die, the first encapsulant having a thickness that extends from at least the intermediate plane to at least a top surface of the GaN-based die;

one or more channels formed in the bottom surface of the leadframe to a depth of at least the intermediate plane;

a second encapsulant disposed within the one or more channels.

2. The electronic package of claim 1 wherein there are two channels formed in the bottom surface of the leadframe.

3. The electronic package of claim 1 wherein portions of the first encapsulant extend to the bottom surface of the leadframe.

4. The electronic package of claim 1 wherein the first terminal is an elongated bar and the plurality of first terminal fingers are attached along a length of the bar and extend outward away from the first terminal in a direction of the second terminal.

5. The electronic package of claim 1 wherein an exposed portion of the first terminal is separated from an exposed portion of the second terminal by a distance of at least 1 millimeter.

6. The electronic package of claim 1 wherein a heat spreader is attached to a top surface of the GaN-based die.

7. The electronic package of claim 6 wherein the heat spreader extends to a top surface of the electronic package.

8. The electronic package of claim 1 wherein a strap is secured to a top surface of the GaN-based die and to the top surface of the leadframe.

9. The electronic package of claim 1 wherein the leadframe has a thickness that is between 50 microns and 250 microns thick.

10. The electronic package of claim 1 wherein a length of the first and the second terminal fingers is greater than a pitch between each of the first terminal fingers and each of the second terminal fingers.

11. A method of forming an electronic package, the method comprising:

providing a metallic leadframe having a thickness extending from a top surface of the leadframe to a bottom surface of the leadframe;

selectively forming a first pattern in the top surface of the leadframe to an intermediate plane having a depth of approximately one half the thickness of the leadframe;

selectively forming a second pattern in the bottom surface of the leadframe to a depth of the intermediate plane;

providing a semiconductor device having a plurality of pads;

mounting the semiconductor device to the top surface of the leadframe using a plurality of electrical interconnects;

forming a first encapsulant around the semiconductor device and within the first and the second patterns;

forming at least one channel in the bottom surface of the leadframe to a depth of at least the intermediate plane; and

disposing a second encapsulant within the at least one channel.

12. The method of claim 11 wherein the second encapsulant is the same material as the first encapsulant.

13. The method of claim 11 wherein the at least one channel is formed by chemically etching the leadframe material.

14. The method of claim 13 wherein the first encapsulant functions as at least one edge of an etching mask.

15. The method of claim 11 wherein the at least one channel is formed by sawing the leadframe material.

16. The method of claim 11 wherein a heat spreader is attached to a top surface of the GaN-based die before forming the first encapsulant.

17. The electronic package of claim 11 wherein a strap is secured to a top surface of the GaN-based die and to the top surface of the leadframe before forming the first encapsulant.

18. A method of forming an electronic package, the method comprising:

providing a metallic leadframe having a thickness extending from a top surface of the leadframe to a bottom surface of the leadframe;

selectively forming a first pattern in the top surface of the leadframe to an intermediate plane having a depth of approximately one half the thickness of the leadframe;

providing a semiconductor device having a plurality of pads;

mounting the semiconductor device to the top surface of the leadframe using a plurality of electrical interconnects;

forming a first encapsulant around the semiconductor device and within the first pattern;

removing at least a portion of the bottom surface of the leadframe to a depth of at least the intermediate plane; and

disposing a dielectric material on a bottom surface of the electronic package.

19. The method of claim 18 wherein the removing at least a portion of the bottom surface of the leadframe comprises forming one or more channels in the bottom surface of the leadframe.

20. The method of claim 19 wherein disposing a dielectric material on a bottom surface of the leadframe comprises disposing an encapsulant material within the one or more channels.

21. The method of claim 18 wherein the removing at least a portion of the bottom surface of the leadframe comprises removing an entire bottom portion of the leadframe to the intermediate plane.

22. The method of claim 21 wherein the dielectric material comprises a dielectric layer disposed on a portion of a bottom surface of the electronic package such that the dielectric layer at least partially defining one or more electronic package interconnects.

23. The method of claim 18 wherein a heat spreader is attached to a top surface of the GaN-based die before forming the first encapsulant.

24. The method of claim 23 wherein the heat spreader extends to a top surface of the electronic package.

25. The electronic package of claim 18 wherein a strap is secured to a top surface of the GaN-based die and to the top surface of the leadframe before forming the first encapsulant.

26. An electronic package comprising:

a leadframe including a first terminal having a plurality of first terminal fingers extending therefrom and a second terminal having a plurality of second terminal fingers extending therefrom wherein the plurality of first terminal fingers are interdigitated with the plurality of second terminal fingers, and a third terminal having at least one third terminal finger;

a GaN-based semiconductor device electrically coupled to a top surface of the leadframe and including a source pad having a plurality of source fingers and a drain pad having a plurality of drain fingers wherein the plurality of source fingers are interdigitated with the plurality of drain fingers, and a gate pad having at least one gate finger;

a plurality of interconnects disposed between the GaN-based die and the leadframe and configured to provide electrical continuity between the plurality of first terminal fingers and the plurality of drain fingers, between the plurality of second terminal fingers and the plurality of source fingers and between the third terminal finger and the at least one gate finger, respectively;

a dielectric layer disposed on a portion of a bottom surface of the electronic package at least partially defining one or more electronic package interconnects; and

an encapsulant layer adhered to the leadframe and encapsulating the GaN-based die, the encapsulant layer having a thickness that extends from at least a top surface of the leadframe to at least a top surface of the GaN-based die;

wherein the first terminal, the second terminal and the third terminal have a first thickness extending from the to surface of the leadframe to a bottom surface of the leadframe; and

wherein the first terminal fingers, the second terminal fingers and the at least one third terminal finger have a second thickness extending from the top surface of the leadframe to an intermediate plane that is located between the top surface and the bottom surface of the leadframe.

27. The electronic package of claim 26 wherein the dielectric layer is a soldermask material.

28. The electronic package of claim 26 wherein the first terminal is an elongated bar and the plurality of first terminal fingers are attached along a length of the bar and extend outward away from the first terminal in a direction of the second terminal.

29. The electronic package of claim 26 wherein the second terminal is an elongated bar and the plurality of second terminal fingers are attached along a length of the bar and extend outward away from the second terminal in a direction of the first terminal.

30. The electronic package of claim 26 wherein the dielectric encapsulant extends to the bottom surface of the electronic package and is disposed within gaps between the plurality of first terminal fingers, the plurality of second terminal fingers and the third terminal finger.

31. The electronic package of claim 26 wherein the dielectric layer has a thickness between 50 microns and 150 microns.

32. The electronic package of claim 26 wherein the leadframe has a thickness that is between 50 microns and 250 microns thick.

33. The electronic package of claim 26 wherein the plurality of interconnects comprise solder.

34. The electronic package of claim 26 wherein the plurality of interconnects comprise copper-based structures secured to the top surface of the leadframe with a solder material.

35. The electronic package of claim 26 wherein the plurality of first terminal fingers and the plurality of the second terminal fingers have a pitch that is 800 microns or less.

36. The electronic package of claim 26 wherein the plurality of first terminal fingers and the plurality of the second terminal fingers have a length that is 1 millimeter or greater.

37. A method of forming an electronic package, the method comprising:

providing a metallic leadframe having a leadframe thickness extending between a top surface of the leadframe and a bottom surface of the leadframe;

selectively forming a first pattern in the top surface of the leadframe to a depth of an intermediate plane disposed between the top surface and the bottom surface of the leadframe;

selectively forming a second pattern in the bottom surface of the leadframe to a depth of the intermediate plane;

providing a semiconductor device having a plurality of pads;

mounting the plurality of the pads of the semiconductor device to the top surface of the leadframe using a plurality of electrical interconnects;

encapsulating the semiconductor device and the top surface of the leadframe with an encapsulant;

forming at least one channel in the bottom surface of the leadframe to a depth of at least the intermediate plane;

disposing a second encapsulant within the at least one channel; and

disposing a dielectric layer on a bottom surface of the electronic package.

38. The electronic package of claim 37 wherein the selective forming of the first pattern and the second pattern are performed with a chemical etching process.

39. The electronic package of claim 37 wherein the encapsulant is disposed within the first pattern to a depth of the intermediate plane.