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Post-passivation interconnect structure

  • US 9,613,914 B2
  • Filed: 12/07/2011
  • Issued: 04/04/2017
  • Est. Priority Date: 12/07/2011
  • Status: Active Grant
First Claim
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1. A semiconductor device, comprising:

  • a semiconductor substrate comprising circuitry and a plurality of metal layers formed between dielectric layers operable to route electrical signals formed therein;

    a passivation layer overlying the semiconductor substrate;

    an interconnect structure overlying and interfacing a top surface of the passivation layer, the interconnect structure comprising a landing pad conductive element and a plurality of dummy conductive elements electrically separated from each other and electrically separated from the landing pad conductive element, wherein the landing pad conductive element and the dummy conductive elements are coplanar;

    a protective layer overlying the interconnect structure and comprising a first opening exposing a portion of the landing pad region and a second opening exposing a portion of the dummy region;

    a metal layer comprising a first portion on a topmost surface of the protective layer and on the exposed portion of the landing pad conductive element and a plurality of second portions on the topmost surface of the protective layer and on the exposed portion of the dummy conductive element, the plurality of second portions of the metal layer being electrically separated from the semiconductor substrate and from the first portion of the metal layer, and wherein the first portion and the plurality of second portions of the metal layer are coplanar; and

    a single bump on the first portion of the metal layer overlying the landing pad conductive element, wherein the second portion of the metal layer is free of a bump;

    wherein each of the plurality of conductive elements adjoins with a respective on of the plurality of second portions of the metal layer to from a plurality of pillars, the plurality of pillars surrounding the single bump in a plan view, and wherein the only bump surrounded by the plurality of pillars is the single bump.

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