Fin liner integration under aggressive pitch

• US 9,613,962 B2
• Filed: 06/03/2016
• Issued: 04/04/2017
• Est. Priority Date: 08/26/2015
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Sung, Min Gyu, Tripathi, Neeraj
• Primary Examiner(s): Ahmad, Khaja
• Application Number:
  US15/172,201
• Publication Number:
  US 20170062429A1
• Time in Patent Office: 305 Days
• Field of Search: None
• CPC Class Codes: H01L 21/02123 the material containing silicon
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/66803 with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin

Abstract

A method of forming a fin liner and the resulting device are provided. Embodiments include forming silicon (Si) fins over negative channel field-effect transistor (nFET) and positive channel field-effect transistor (pFET) regions of a substrate, each of the Si fins having a silicon nitride (SiN) cap; forming a SiN liner over the Si fins and SiN caps; forming a block mask over the pFET region; removing the SiN liner in the nFET region; removing the block mask in the pFET region; forming a diffusion barrier liner over the Si fins; forming a dielectric layer over and between the Si fins; planarizing the dielectric layer down to the SiN caps in the nFET region; and recessing the dielectric layer to expose an upper portion of the Si fins.

Claims

1. A device comprising:

silicon (Si) fins formed over negative channel field-effect transistor (nFET) and positive channel field-effect transistor (pFET) regions of a substrate;

a silicon dioxide (SiO₂) liner over the Si fins in the nFET region;

a dielectric layer disposed between a lower portion of the Si fins, leaving an exposed upper portion of the Si fins; and

a siliconborocarbonitride (SiBCN) liner disposed between the SiO₂ liner and the dielectric layer, and directly on a bottom surface of the dielectric layer.

2. The device according to claim 1, wherein the exposed upper portion of the Si fins in the pFET region comprises silicon germanium (SiGe).

3. The device according to claim 2, wherein the SiO₂ liner in the nFET region is disposed between the SiBCN liner and the Si fins.

4. The device according to claim 3, wherein the SiO₂ liner has a thickness of 1 nanometer (nm) on opposing sides of the Si fins.

5. The device according to claim 1, further comprising:

a SiN liner disposed on the Si fins in the pFET region between the SiBCN liner and the Si fins.

6. The device according to claim 1, wherein the nFET channel region is doped with boron (B).

7. The device according to claim 1, wherein the dielectric layer comprises SiO₂.

8. A device comprising:

silicon (Si) fins formed over negative channel field-effect transistor (nFET) and positive channel field-effect transistor (pFET) regions of a substrate, each of the Si fins having a silicon nitride (SiN) cap;

an oxide liner formed over the Si fins in the nFET region;

a silicon dioxide (SiO₂) dielectric layer disposed between the Si fins, leaving an exposed upper portion of the Si fins; and

a diffusion barrier liner disposed between the oxide liner and the SiO₂ dielectric layer, and directly on a bottom surface of the SiO₂ dielectric layer.

9. The device according to claim 8, wherein the diffusion barrier liner comprises siliconborocarbonitride (SiBCN).

10. The device according to claim 8, wherein the SiO₂ dielectric layer is densified by way of annealing.

11. The device according to claim 8, wherein an upper portion of the Si fins in the pFET region comprise silicon germanium (SiGe).

12. The device according to claim 9, wherein the oxide liner comprises SiO₂ disposed between the SiBCN liner and the Si fins.

13. The device according to claim 12, wherein the SiO₂ liner has a thickness of 1 nanometer (nm) on opposing sides of the Si fins.

14. The device according to claim 8, further comprising:

a SiN liner disposed on the Si fins in the pFET region between the diffusion barrier liner and the Si fins.

15. The device according to claim 8, wherein the nFET channel region is doped with boron (B).

16. A device comprising:

silicon (Si) fins formed over negative channel field-effect transistor (nFET) and positive channel field-effect transistor (pFET) regions of a substrate,

wherein an upper portion of the Si fins in the pFET region comprise silicon germanium (SiGe);

a silicon dioxide (SiO₂) liner over the Si fins in the nFET region;

a SiO₂ dielectric layer disposed between a lower portion of the Si fins, leaving an exposed upper portion of the Si fins;

a SiN liner disposed on the Si fins in the pFET region between a diffusion barrier liner and the Si fins; and

a siliconborocarbonitride (SiBCN) liner disposed between the SiO₂ liner and the SiO₂ dielectric layer in the nFET region, between the SiN liner and the SiO₂ dielectric layer in the pFET region, and directly on a bottom surface of the SiO₂ dielectric layer.

17. The device according to claim 16, wherein the SiO₂ liner in the nFET region is disposed between the SiBCN liner and the Si fins.

18. The device according to claim 17, wherein the SiO₂ liner has a thickness of 1 nanometer (nm) on opposing sides of the Si fins.

19. The device according to claim 16, wherein the nFET channel region is doped with boron (B).

20. The device according to claim 16, wherein the pFET channel region is doped with phosphorous (P).