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Fin liner integration under aggressive pitch

  • US 9,613,962 B2
  • Filed: 06/03/2016
  • Issued: 04/04/2017
  • Est. Priority Date: 08/26/2015
  • Status: Active Grant
First Claim
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1. A device comprising:

  • silicon (Si) fins formed over negative channel field-effect transistor (nFET) and positive channel field-effect transistor (pFET) regions of a substrate;

    a silicon dioxide (SiO2) liner over the Si fins in the nFET region;

    a dielectric layer disposed between a lower portion of the Si fins, leaving an exposed upper portion of the Si fins; and

    a siliconborocarbonitride (SiBCN) liner disposed between the SiO2 liner and the dielectric layer, and directly on a bottom surface of the dielectric layer.

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