Spacers with rectangular profile and methods of forming the same

• US 9,614,053 B2
• Filed: 12/05/2013
• Issued: 04/04/2017
• Est. Priority Date: 12/05/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Yu-Sheng, Lee, Chung-Ju, Bao, Tien-I
• Primary Examiner(s): Miyoshi, Jesse Y
• Assistant Examiner(s): Hoang, Tuan A
• Application Number:
  US14/097,579
• Publication Number:
  US 20150162416A1
• Time in Patent Office: 1,216 Days
• CPC Class Codes: H01L 21/02118 carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC polymers per se C08G, photoresist per se G03F
• CPC Class Codes: H01L 21/0212 the material being fluoro carbon compounds, e.g.(CFx) n, (CHxFy) n or polytetrafluoroethylene
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A method includes forming a spacer layer on a top surface and sidewalls of a patterned feature, wherein the patterned feature is overlying a base layer, A protection layer is formed to contact a top surface and a sidewall surface of the spacer layer. The horizontal portions of the protection layer are removed, wherein vertical portions of the protect layer remain after the removal. The spacer layer is etched to remove horizontal portions of the spacer layer, wherein vertical portions of the spacer layer remain to form parts of spacers.

Claims

1. A method comprising:

forming a spacer layer on a first top surface and sidewalls of a patterned feature, wherein the patterned feature is overlying a base layer, wherein the spacer layer comprises first horizontal portions directly on the base layer, and the first horizontal portions cover an entire top surface of the base layer, with the entire top surface being between the patterned feature and a neighboring patterned feature;

forming a protection layer contacting a second top surface and a sidewall surface of the spacer layer, wherein the protection layer comprises second horizontal portions over the first horizontal portions;

removing the second horizontal portions of the protection layer, wherein vertical portions of the protection layer remain after the removing;

etching the spacer layer using the remaining vertical portions of the protection layer as an etching mask to remove all horizontal portions of the spacer layer, wherein the vertical portions of the spacer layer and the remaining vertical portions of the protection layer remain to form spacers;

after the etching the spacer layer, removing the patterned feature;

etching the base layer and the vertical portions of the protection layer to form a trench in the base layer, wherein the spacers are used as an etching mask;

filling the trench with a metal; and

removing the spacers.

2. The method of claim 1, wherein the forming the protection layer comprises performing a nitridation to convert a surface layer of the spacer layer into the protection layer, wherein a top surface of a horizontal portion of the spacer layer is nitridated as a horizontal portion of the protection layer.

3. The method of claim 1, wherein the forming the protection layer comprises performing an oxidation to convert a surface layer of the spacer layer into the protection layer.

4. The method of claim 1, wherein the forming the protection layer comprises depositing the protection layer over the spacer layer, and wherein a process gas for the depositing comprises CH₄ and N₂.

5. The method of claim 1, wherein the forming the protection layer comprises depositing the protection layer over the spacer layer, and wherein a process gas for the depositing comprises CH₂F₂.

6. The method of claim 1, wherein the patterned feature comprises a gate dielectric and a gate electrode over the gate dielectric, and wherein the base layer comprises a semiconductor substrate.

7. A method comprising:

forming a spacer layer comprising;

a top portion on a top surface of a first and a second patterned feature;

vertical portions on opposite sidewalls of the first and the second patterned features; and

first horizontal portions with bottom surfaces contacting top surface of a base layer, wherein the first horizontal portions extend from the first patterned feature to the second patterned feature;

performing a nitridation or an oxidation to convert a surface layer of the spacer layer into a protection layer, wherein a bottom layer of the spacer layer remains after the nitridation or the oxidation;

performing an anisotropic etching to remove a horizontal portion of the protection layer, wherein vertical portions of the protection layer remains on sidewalls of remaining portions of the vertical portions of the spacer layer; and

removing a portion of the bottom layer in the top portion of the spacer layer using the vertical portions of the protection layer as an etching mask, wherein remaining portions of the vertical portions of the spacer layer and the vertical portions of the protection layer remain as masks;

removing the first and the second patterned features;

etching the base layer using the masks as an etching mask; and

removing the remaining portions of the vertical portions of the spacer layer and the vertical portions of the protection layer.

8. The method of claim 7, wherein after the top portion of the spacer layer is removed, the spacer layer does not have any portion overlapped by the vertical portions of the protection layer, with vertical portions of the spacer layer remaining, wherein the vertical portions of the protection layer have bottom surfaces higher than bottom surfaces of the remaining vertical portions of the spacer layer.

9. The method of claim 7, wherein the etching the base layer generates recesses in the base layer.

10. The method of claim 9 further comprising filling the recesses with a metallic material.

11. The method of claim 7, wherein the anisotropic etching is performed using a first etchant gas, and the removing the top portion of the spacer layer is performed using a second etchant gas different from the first etchant gas.

12. The method of claim 7, wherein the nitridation or the oxidation comprises an oxidation.

13. The method of claim 10 further comprising filling entireties of the recesses with conductive materials.