Semiconductor device and method for fabricating the same

• US 9,614,055 B2
• Filed: 02/18/2015
• Issued: 04/04/2017
• Est. Priority Date: 06/28/2000
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Inagawa, Hiroshi, Machida, Nobuo, Ooishi, Kentaro
• Primary Examiner(s): DIALLO, MAMADOU L
• Application Number:
  US14/624,987
• Publication Number:
  US 20150179763A1
• Time in Patent Office: 776 Days
• Field of Search: 438268-274
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0611 for increasing or controlling the breakdown voltage of reverse biased devices H01L29/0661 takes precedence
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7804 the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.

Claims

1. A method of manufacturing a semiconductor device including a MISFET forming region of a semiconductor substrate and a peripheral region of the semiconductor substrate, comprising steps of:

(a) forming a first semiconductor layer of a first conductive type in the semiconductor substrate;

(b) forming a field insulating film in the peripheral region;

(c) forming a well region of the second conductive type opposite to the first conductive type in the peripheral region such that the well region is also formed under the field insulating film;

(d) forming a first trench in the MISFET forming region, and forming a second trench in the peripheral region such that the second trench penetrates the well region and a bottom of the second trench is located at the first semiconductor layer, wherein the first and second trenches are unified;

(e) forming a first gate insulating film in the first trench, and forming a second gate insulating film in the second trench;

(f) forming a gate electrode in the first trench through the first gate insulating film, and forming a gate wiring formed in the second trench through the second gate insulating film such that the gate wiring is also formed over the field insulating film, wherein the gate electrode and the gate wiring are unified;

(g) after the step (f), forming a second semiconductor layer of the second conductive type in the first semiconductor layer of the MISFET forming region;

(h) after the step (f), forming a third semiconductor layer of the first conductive type in the second semiconductor layer;

(i) after the steps (g) and (h), forming a contact hole formed in the second and third semiconductor layers such that a bottom of the contact hole is located at the second semiconductor layer; and

(j) forming a source wiring in the contact hole and connected to the second and third semiconductor layers.

2. The method of manufacturing a semiconductor device according to claim 1,

wherein an impurity concentration of the well region is lower than an impurity concentration of the second semiconductor layer.

3. The method of manufacturing a semiconductor device according to claim 1,

wherein a depth of the well region is different form a depth of the second semiconductor layer.

4. The method of manufacturing a semiconductor device according to claim 3,

wherein the depth of the well region is lower than the depth of the second semiconductor layer.

5. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a fourth semiconductor layer of the second conductive type in the second semiconductor layer which is arranged at a bottom of the contact hole between the steps (i) and (j),

wherein an impurity concentration of the fourth semiconductor layer is higher than an impurity concentration of the second semiconductor layer.

6. The method of manufacturing a semiconductor device according to claim 1,

wherein the source wiring is connected to an upper surface of the third semiconductor layer outside the second trench and a side surface of the third semiconductor layer inside the second trench.

7. The method of manufacturing a semiconductor device according to claim 1,

wherein the first semiconductor region serves a drain region of a MISFET,

wherein the second semiconductor region serves a channel region of the MISFET, and

wherein the third semiconductor region serves a source region of the MISFET.

8. The method of manufacturing a semiconductor device according to claim 1,

wherein the first conductive type is an n-type, and

wherein the second conductive type is a p-type.