Semiconductor device provided with an IE type trench IGBT

• US 9,614,066 B2
• Filed: 04/26/2016
• Issued: 04/04/2017
• Est. Priority Date: 05/22/2014
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Matsuura, Hitoshi
• Primary Examiner(s): NGO, NGAN V
• Application Number:
  US15/138,687
• Publication Number:
  US 20160240643A1
• Time in Patent Office: 343 Days
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0804 Emitter regions of bipolar transistors
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41708 Emitter or collector electrodes for bipolar transistors
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A switching loss is prevented from being deteriorated by suppressing increase in a gate capacitance due to a cell shrink of an IE type trench gate IGBT. A cell formation region is configured of a linear active cell region, a linear hole collector cell region, and a linear inactive cell region between them. Then, upper surfaces of the third and fourth linear trench gate electrodes which are formed so as to sandwich both sides of the linear hole collector cell region and electrically connected to an emitter electrode are positioned to be lower than upper surfaces of the first and second linear trench gate electrodes which are formed so as to sandwich both sides of the linear active cell region and electrically connected to a gate electrode.

Claims

1. A semiconductor device provided with an IE type trench IGBT includes the followings:

(a) a semiconductor substrate which has a first main surface and a second main surface opposite to the first main surface;

(b) a collector region which is formed in the semiconductor substrate and which has a first conductivity type;

(c) a drift region which is formed in the semiconductor substrate on the collector region and which has a second conductivity type different from the first conductivity type;

(d) a plurality of linear unit cell regions which are formed along a first direction in the semiconductor substrate on the drift region;

(e) a gate electrode provided on the first main surface side;

(f) an emitter electrode provided on the first main surface side; and

(g) a collector electrode provided on the second main surface side,

the linear unit cell region includes;

(d1) a linear hybrid cell region provided from the first main surface to inside;

(d2) a first linear hybrid sub cell region and a second linear hybrid sub cell region provided in the linear hybrid cell region so as to be symmetrical to each other in the first direction;

(d3) a first trench which is formed at a boundary between the first linear hybrid sub cell region and the second linear hybrid sub cell region so as to have a first depth from the first main surface;

(d4) a first linear trench gate electrode which is electrically connected to the gate electrode and which is formed inside the first trench;

(d5) a second trench and a third trench which are formed so as to sandwich both sides of the linear hybrid cell region in the first direction and so as to have the first depth from the first main surface;

(d6) a second linear trench gate electrode and a third linear trench gate electrode which are electrically connected to the emitter electrode and which are formed inside the second trench and the third trench, respectively;

(d7) an emitter region of the second conductivity type which is formed in a center part of the linear hybrid cell region so as to be in contact with the first trench and so as to have a second depth from the first main surface;

(d8) a body region of the first conductivity type which is formed below the emitter region so as to have a third depth deeper than the second depth from the first main surface;

(d9) a linear inactive cell region provided on both sides of the linear hybrid cell region in the first direction via the second trench and the third trench;

(d10) a floating region of the first conductivity type which is formed in the linear inactive cell region so as to have a fourth depth from the first main surface;

(d11) a first contact groove which is formed in a region on the second trench side of the first linear hybrid sub cell region so as to overlap with the second trench when seen in a plan view and so as to have a fifth depth shallower than the third depth from the first main surface; and

(d12) a second contact groove which is formed in a region on the third trench side of the second linear hybrid sub cell region so as to overlap with the third trench when seen in a plan view and so as to have the fifth depth;

wherein, further, upper surfaces of the second linear trench gate electrode and the third linear trench gate electrode are positioned to be lower than an upper surface of the first linear trench gate electrode.

2. A semiconductor device provided with an IE type trench IGBT includes the followings:

(a) a semiconductor substrate which has a first main surface and a second main surface opposite to the first main surface;

(b) a collector region which is formed in the semiconductor substrate and which has a first conductivity type;

(c) a drift region which is formed in the semiconductor substrate on the collector region and which has a second conductivity type different from the first conductivity type;

(d) a plurality of linear unit cell regions which are formed along a first direction in the semiconductor substrate on the drift region;

(e) a gate electrode provided on the first main surface side;

(f) an emitter electrode provided on the first main surface side; and

(g) a collector electrode provided on the second main surface side,

the linear unit cell region includes;

(d1) a first trench and a second trench which are formed so as to sandwich both sides of the linear unit cell region in the first direction and so as to have a first depth from the first main surface;

(d2) a first linear trench gate electrode and a second linear trench gate electrode which are electrically connected to the gate electrode and which are formed inside the first trench and the second trench, respectively;

(d3) a plurality of third trenches which are formed between the first trench and the second trench so as to be separated from each other, and which has the first depth;

(d4) a plurality of third linear trench gate electrodes which are electrically connected to the emitter electrode and which are formed inside the plurality of third trenches, respectively;

(d5) a first emitter region and a second emitter region which are formed so as to have a second depth from the first main surface and so as to be in contact with the first trench and the second trench, respectively; and

(d6) a first body region and a second body region of the first conductivity type which are formed below the first emitter region and the second emitter region so as to have a third depth deeper than the second depth from the first main surface, respectively;

wherein, further, an upper surface of the plurality of third linear trench gate electrodes is positioned to be lower than upper surfaces of the first linear trench gate electrode and the second linear trench gate electrode.