System and method for deskewing output clock signals
First Claim
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1. A method for deskewing output clock signals, the method comprising:
- determining, at a clock generator, a transit time of each of a plurality of traces, each of the plurality of traces coupled between one of a plurality of clock generator outputs and one of a plurality of clock receivers;
determining a longest transit time of the transit times of each of the plurality of traces;
determining a difference between the longest transit time and the transit time of each of the plurality of traces to identify a time delay for each of the plurality of clock generator outputs; and
adding the time delay for each of the plurality of clock generator outputs to a output clock signal transmitted from each of the plurality of clock generator outputs.
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Abstract
A clock generator having deskewed outputs signals wherein a transit time of each of a plurality of traces coupled to the clock generator outputs are determined and the longest trace is identified as the trace having the longest transit time. A time delay is then added to an output clock signal at each of the clock generator outputs that are not coupled to the longest trace. The addition of the time delay for each of the clock generator outputs is effective in automatically deskewing the clock generator outputs.
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Citations
20 Claims
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1. A method for deskewing output clock signals, the method comprising:
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determining, at a clock generator, a transit time of each of a plurality of traces, each of the plurality of traces coupled between one of a plurality of clock generator outputs and one of a plurality of clock receivers; determining a longest transit time of the transit times of each of the plurality of traces; determining a difference between the longest transit time and the transit time of each of the plurality of traces to identify a time delay for each of the plurality of clock generator outputs; and adding the time delay for each of the plurality of clock generator outputs to a output clock signal transmitted from each of the plurality of clock generator outputs. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A circuit for deskewing output signals of a clock generator, the circuit comprising:
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a plurality of line length to digital converter circuits, each of the line length to digital converter circuits coupled to one of a plurality of clock generator outputs of a clock generator and each of the line length to digital converter circuits configured to determine a transit time of a trace coupled between a clock generator output of the plurality of clock generator outputs and one of a plurality of clock receivers; a control circuit coupled to each of the plurality of line length to digital converter circuits, the control circuit configured to determine a longest transit time of the transit times determined by each of the line length to digital converter circuits and to determine a difference between the longest transit time and each determined transit time of a trace identify a time delay for each of the plurality of clock generator outputs; and a plurality of digitally controlled delay elements, each of the plurality of digitally controlled delay elements coupled to the control circuit and to one of the plurality of clock generator outputs and each of the digitally controlled delay elements configured to receive the time delay for the clock generator output that the digitally controlled delay element is coupled to from the control circuit and to add the received time delay for the clock generator output to an output clock signal transmitted from the clock generator output. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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20. An integrated circuit clock generator having deskewed output signals, the clock generator comprising:
a clock skew equalization circuit comprising; a plurality of line length to digital converter circuits, each of the line length to digital converter circuits coupled to one of a plurality of clock generator outputs of a clock generator and each of the line length to digital converter circuits configured to determine a transit time of a trace coupled between a clock generator output of the plurality of clock generator outputs and one of a plurality of clock receivers; a control circuit coupled to each of the plurality of line length to digital converter circuits, the control circuit configured to determine a longest transit time of the determined transit times and to determine a difference between the longest transit time and each determined transit time of a trace to identify a time delay for each of the plurality of clock generator outputs; and a plurality of digitally controlled delay elements, each of the plurality of digitally controlled delay elements coupled to the control circuit and to one of the plurality of clock generator outputs and each of the digitally controlled delay elements configured to receive the time delay for the clock generator output that the digitally controlled delay element is coupled to and to add the received time delay for the clock generator output to an output clock signal transmitted from the clock generator output.
Specification