Driver IC of a display panel waiting a predetermined time before supplying vertical synchronization signal (VSYNC) after sleep-out command is received

• US 9,619,007 B2
• Filed: 12/04/2013
• Issued: 04/11/2017
• Est. Priority Date: 12/07/2012
• Status: Active Grant

• Current Assignee: Synaptics Japan GK (Synaptics Incorporated)
• Original Assignee: Synaptics Japan GK (Synaptics Incorporated)
• Inventors: Mizuno, Toshio, Kobayashi, Miho, Sakurai, Junpei
• Primary Examiner(s): LEE, THOMAS C
• Assistant Examiner(s): Poudel, Santosh R
• Application Number:
  US14/097,174
• Publication Number:
  US 20140164806A1
• Time in Patent Office: 1,224 Days
• CPC Class Codes: G06F 1/3265 Power saving in display device
• CPC Class Codes: G09G 2330/02 Details of power systems and of start or stop of display operation
• CPC Class Codes: G09G 2330/022 in absence of operation, e.g. no data being entered during a predetermined time
• CPC Class Codes: G09G 2330/025 Reduction of instantaneous peaks of current
• CPC Class Codes: G09G 2330/026 Arrangements or methods related to booting a display
• CPC Class Codes: G09G 2330/027 Arrangements or methods related to powering off a display
• CPC Class Codes: G09G 3/3696 Generation of voltages supplied to electrode drivers
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

An integrated circuit device includes first and second integrated circuits and a power supply line. The first integrated circuit includes a first power supply circuit, a timing generation circuit generating a synchronization signal, and a first power supply control section. The second integrated circuit includes a second power supply circuit and a second power supply control section. The power supply line electrically connects the outputs of the first and second power supply circuit. The first and second power supply control sections are each configured to start the operations of the first and second power supply circuits, respectively, in response to a start of a supply of the synchronization signal after a sleep-out command is supplied thereto. The timing generation circuit starts supplying the synchronization signal after a predetermined waiting time elapses after the sleep-out command is supplied to the first integrated circuit.

Claims

1. An integrated circuit device, comprising:

a first integrated circuit including;

a first power supply circuit;

a timing generation circuit generating a vertical synchronization signal defining each vertical synchronization period; and

a first power supply control section controlling operation timing of said first power supply circuit;

a second integrated circuit including;

a second power supply circuit; and

a second power supply control section controlling operation timing of said second power supply circuit; and

a power supply line electrically connecting outputs of said first and second power supply circuits,

wherein said first and second integrated circuits are adapted to a sleep mode,

wherein an operation of said first power supply circuit is stopped when said first integrated circuit is placed into the sleep mode,

wherein an operation of said second power supply circuit is stopped when said second integrated circuit is placed into the sleep mode,

wherein said vertical synchronization signal is supplied to said first and second power supply control sections,

wherein said first power supply control section is configured to start the operation of said first power supply circuit in response to a start of a supply of said vertical synchronization signal after a first sleep-out command to get out of the sleep mode is supplied to said first integrated circuit,

wherein said second power supply control section is configured to start the operation of said second power supply circuit in response to a start of a supply of said vertical synchronization signal after a second sleep-out command to get out of the sleep mode is supplied to said second integrated circuit, and

wherein said timing generation circuit starts supplying said vertical synchronization signal after a predetermined waiting time elapses after said first sleep-out command is supplied to said first integrated circuit.

2. The integrated circuit device according to claim 1, wherein said first power supply circuit includes a first output switch which connects the output of said first power supply circuit to a ground terminal when the operation of said first power supply circuit is stopped, and

wherein said second power supply circuit includes a second output switch which connects the output of said second power supply circuit to a ground terminal when the operation of said second power supply circuit is stopped.

3. The integrated circuit device according to claim 1, further comprising a host which supplies the first sleep-out command to the first integrated circuit and the second sleep-out command to the second integrated circuit.

4. A panel display device, comprising:

a display panel;

first and second drivers driving said display panel; and

a power supply line,

wherein said first driver includes;

a first power supply circuit;

a timing generation circuit generating a vertical synchronization signal defining each vertical synchronization period; and

a first power supply control section controlling operation timing of said first power supply circuit;

wherein said second driver includes;

a second power supply circuit; and

a second power supply control section controlling operation timing of said second power supply circuit;

wherein said power supply line electrically connects outputs of said first and second power supply circuits,

wherein said first and second drivers are adapted to a sleep mode,

wherein an operation of said first power supply circuit is stopped when said first driver is placed into the sleep mode,

wherein an operation of said second power supply circuit is stopped when said second driver is placed into the sleep mode,

wherein said vertical synchronization signal is supplied to said first and second power supply control sections,

wherein said first power supply control section is configured to start the operation of said first power supply circuit in response to a start of a supply of said vertical synchronization signal after a first sleep-out command to get out of the sleep mode is supplied to said first driver,

wherein said second power supply control section is configured to start the operation of said second power supply circuit in response to a start of a supply of said vertical synchronization signal after a second sleep-out command to get out of the sleep mode is supplied to said second driver,

wherein said timing generation circuit starts supplying said vertical synchronization signal after a predetermined waiting time elapses after said first sleep-out command is supplied to said first driver.

5. The panel display device according to claim 4, wherein a time duration of said predetermined waiting time is equal to or longer than a time duration of one frame period defined as a cycle period of said vertical synchronization signal.

6. The panel display device according to claim 4, wherein said first power supply circuit includes a first output switch which connects the output of said first power supply circuit to a ground terminal when the operation of said first power supply circuit is stopped, and

wherein said second power supply circuit includes a second output switch which connects the output of said second power supply circuit to a ground terminal when the operation of said second power supply circuit is stopped.

7. The panel display device according to claim 4,

wherein said first driver includes a first driving circuit operating on a first power supply voltage outputted from said first power supply circuit to drive said display panel, and

wherein said second driver includes a second driving circuit operating on a second power supply voltage outputted from said second power supply circuit to drive said display panel.

8. The panel display device according to claim 4, further comprising a host which supplies the first sleep-out command to the first driver and the second sleep-out command to the second driver.

9. A display panel driver configured to drive a display panel and adapted to a sleep mode, comprising:

a power supply circuit;

a timing generation circuit generating a vertical synchronization signal defining each vertical synchronization period; and

a power supply control section controlling operation timing of said power supply circuit,

wherein an operation of said power supply circuit is stopped when said display panel driver is placed into the sleep mode,

wherein said vertical synchronization signal is supplied to said power supply control section,

wherein said power supply control section is configured to start the operation of said power supply circuit in response to a start of a supply of said vertical synchronization signal after a sleep-out command to get out of the sleep mode is supplied to said display panel driver,

wherein said timing generation circuit starts supplying said vertical synchronization signal after a predetermined waiting time elapses after said sleep-out command is supplied to said display panel driver;

wherein the sleep-out command is supplied from a host to the display panel driver, and wherein the timing generation circuit externally outputs the vertical synchronization signal to a different display panel driver which is different than the host and configured to drive the display panel.

10. The display panel driver according to claim 9, wherein a time duration of said predetermined waiting time is equal to or longer than a time duration of one frame period defined as a cycle period of said vertical synchronization signal.

11. The display panel driver according to claim 9, wherein said power supply circuit comprises a plurality of power supply circuits, and wherein one power supply circuit of said plurality of power supply circuits assumes a master role to provide said vertical synchronization signal to remaining power supply circuits.