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Pseudo-random bit sequence generator

  • US 9,619,206 B2
  • Filed: 04/23/2014
  • Issued: 04/11/2017
  • Est. Priority Date: 05/07/2009
  • Status: Active Grant
First Claim
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1. Bit sequence generation circuitry comprising:

  • first register circuitry that stores a current state data; and

    first combinational logic circuitry that;

    receives the current state data from the first register circuitry;

    determines a next state data in a single clock cycle by processing the current state data through the first combinational logic circuitry, wherein the next state data is equivalent to an n-bit datapath that would be generated by a linear feedback shift register as a result of n bit-shifts through the linear feedback shift register; and

    outputs the next state data;

    wherein a critical path of the first combinational logic circuitry comprises a maximum number of logic gates for data to travel through to process from the current state data to the next state data, wherein the maximum number of logic gates is fewer than a number of logic gates that would be applied by the linear feedback shift register over the n bit-shifts through the linear feedback shift register.

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