Enforcing different operational configurations for different tasks for failure rate based control of processors
First Claim
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1. A method comprising:
- specifying a plurality of different maximum failure rates each corresponding to a different task of a plurality of tasks executing at a given time on a processor;
determining a different operational configuration each including a different minimum voltage for each of the plurality of specified different maximum failure rates;
enforcing a plurality of processor logic each executing a different one of the plurality of tasks to operate at a given time on the processor according to the different corresponding determined operational configurations including enforcing the plurality of processor logic to operate at voltages not less than the different corresponding determined minimum voltages.
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Abstract
A method of an aspect includes determining a different operational configuration for each of a plurality of different maximum failure rates. Each of the different maximum failure rates corresponds to a different task of a plurality of tasks. The method also includes enforcing a plurality of logic each executing a different task of the plurality of tasks to operate according to the different corresponding determined operational configuration. Other methods, apparatus, and systems are also disclosed.
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Citations
23 Claims
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1. A method comprising:
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specifying a plurality of different maximum failure rates each corresponding to a different task of a plurality of tasks executing at a given time on a processor; determining a different operational configuration each including a different minimum voltage for each of the plurality of specified different maximum failure rates; enforcing a plurality of processor logic each executing a different one of the plurality of tasks to operate at a given time on the processor according to the different corresponding determined operational configurations including enforcing the plurality of processor logic to operate at voltages not less than the different corresponding determined minimum voltages. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A processor comprising:
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a plurality of logical processors to each execute a different corresponding task of a plurality of tasks; logic to determine a different operational configuration including a different minimum voltage for each of a plurality of specified different maximum failure rates, each of the specified different maximum failure rates to correspond to a different task of the plurality of tasks that are to execute at a given time on the processor; and logic to enforce the plurality of logical processors to operate at a given time on the processor according to the different corresponding determined operational configurations including at voltages not less than the different corresponding minimum voltages when executing the corresponding tasks. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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21. A system comprising:
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an interconnect; a processor coupled with the interconnect, the processor including; a plurality of logical processors to each execute a different corresponding task of a plurality of tasks; logic to determine a different operational configuration including a different minimum voltage for each of a plurality of specified different maximum failure rates for a processor, each of the specified different maximum failure rates to correspond to a different task of the plurality of tasks that are to execute at a given time on the processor; and logic to enforce the plurality of logical processors to operate at a given time on the processor according to the different corresponding determined operational configurations including at voltages not less than the different corresponding minimum voltages when executing the corresponding tasks; and a dynamic random access memory (DRAM) coupled with the interconnect. - View Dependent Claims (22, 23)
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Specification