Memory write protection for memory corruption detection architectures

• US 9,619,313 B2
• Filed: 06/19/2015
• Issued: 04/11/2017
• Est. Priority Date: 06/19/2015
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Stark, Tomer, Gabor, Ron, Tal, Ady, Nuzman, Joseph
• Primary Examiner(s): Ehne, Charles
• Application Number:
  US14/745,172
• Publication Number:
  US 20160371139A1
• Time in Patent Office: 662 Days
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/0766 Error or fault reporting or storing
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 11/0787 Storage of error reports, e.g. persistent data storage, storage using memory protection
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163
• CPC Class Codes: G06F 12/1425 the protection being physical, e.g. cell, word, block
• CPC Class Codes: G06F 12/1441 for a range
• CPC Class Codes: G06F 12/1466 Key-lock mechanism
• CPC Class Codes: G06F 2201/80 Database-specific techniques
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/1052 Security improvement

Abstract

Memory corruption detection technologies are described. A processing system can include a processor core including a register to store an address of a memory corruption detection (MCD) table. The processor core can receive, from an application, a memory store request to store data in a first portion of a contiguous memory block of the memory object of a memory. The memory store request comprises a first pointer indicating a first location of the first portion in the memory block to store the data. The processor core can retrieve, from the MCD table, a write protection indicator that indicates a first protection mode of the first portion. The processor core can send, to the application, a fault message when a fault event associated with the first portion occurs based on the first protection mode of the first portion.

Claims

1. A processing system comprising:

a processor core comprising a register to store an address of a memory corruption detection (MCD) table, wherein the processing core is to;

receive, from an application, an allocation request for allocation of a memory object with a contiguous memory block in memory;

allocate the contiguous memory block for the memory object in view of a size of the memory object requested;

write, into the MCD table, a MCD metadata word, wherein the MCD metadata word comprises;

a first MCD unique identifier (ID) associated with the contiguous memory block; and

a write protection indicator that indicates a first protection mode of a first portion of the contiguous memory block;

receive, from the application, a memory store request to store data in the first portion of the contiguous memory block of the memory object of the memory, wherein the memory store request comprises a first pointer indicating a first location of the first portion in the memory block to store the data;

retrieve, from the MCD table, the write protection indicator that indicates the first protection mode of the first portion; and

send, to the application, a fault message when a fault event associated with the first portion occurs based on the first protection mode of the first portion.

2. The processing system of claim 1, wherein the contiguous memory block comprises the first portion of the contiguous memory block and a second portion of the contiguous memory block, wherein:

the first protection mode is a write protection mode; and

a second protection mode of the second portion is a non-write protection mode.

3. The processing system of claim 2, wherein the fault event associated with the first portion is an event where the processor core receives, from the application, a memory store request to write data to the first portion.

4. The processing system of claim 2, wherein the first portion stores at least one of allocation metadata, linked-list pointers, or a return address of a function for a stack.

5. The processing system of claim 1, wherein:

the memory store request further comprises;

a second MCD unique ID; and

a second pointer indicating a second location in the memory of the memory object; and

the processing core is further to;

compare the first MCD unique ID to the second MCD unique ID; and

write the data to the first portion when the first MCD unique ID matches the second MCD unique ID.

6. The processing system of claim 5, wherein the processing core is further to send the fault message when the first MCD unique ID does not match the second MCD unique ID.

7. The processing system of claim 1, wherein the contiguous memory block is 64 bytes in size.

8. The processing system of claim 7, wherein the MCD metadata word comprises a first byte and a second byte, and wherein:

the first byte comprises;

the first MCD unique ID, a mode indicator of the second byte, and a reserved bit; and

the second byte comprises byte level granularity detection information and the write protection indicator.

9. A processing system comprising:

a processor core comprising a register to store an address of a memory corruption detection (MCD) table, wherein the processing core is to;

receive, from an application, a memory store request to store data in a first portion of a contiguous memory block of the memory object of a memory, wherein the memory store request comprises a first pointer indicating a first location of the first portion in the memory block to store the data;

retrieve, from the MCD table, a write protection indicator that indicates a first protection mode of the first portion; and

send, to the application, a fault message when a fault event associated with the first portion occurs based on the first protection mode of the first portion.

10. The processing system of claim 9, wherein the processing core is further to:

receive, from the application, an allocation request for an allocation of the memory object with the contiguous memory block in the memory;

allocate the contiguous memory block for the memory object in view of a size of the memory object requested; and

write, into the MCD table, a MCD metadata word, wherein the MCD metadata word comprises;

a first MCD unique identifier (ID) associated with the contiguous memory block; and

the write protection indicator that indicates the first protection mode of the first portion of the contiguous memory block.

11. The processing system of claim 10, wherein:

the memory store request further comprises;

a second MCD unique ID; and

a second pointer indicating a second location in the memory of the memory object; and

the processing core is further to;

compare the first MCD unique ID to the second MCD unique ID; and

write the data to the first portion when the first MCD unique ID matches the second MCD unique ID.

12. The processing system of claim 9, wherein the contiguous memory block comprises the first portion of the contiguous memory block and a second portion of the contiguous memory block, wherein:

the first protection mode of the first portion is a write protection mode; and

a second protection mode of the second portion is a non-write protection mode.

13. The processing system of claim 12, wherein the fault event associated with the first portion is an event where the processor core receives, from the application, a memory store request to write data to the first portion.

14. The processing system of claim 12, wherein the first portion stores at least one of allocation metadata, linked-list pointers, or a return address of a function for a stack.

15. A system on a chip (SoC) comprising:

a processor;

a memory device, coupled to the processor, to store data from an application, wherein the memory comprises a memory corruption detection (MCD) table and a memory object; and

a memory controller coupled to the memory device, the memory controller to;

receive, from the application, an allocation request for an allocation of the memory object with a contiguous memory block in the memory;

allocate the contiguous memory block for the memory object in view of a size of the memory object requested; and

write, into the MCD table, a MCD metadata word with a write protection indicator that indicates a first protection mode of a first portion of the contiguous memory block.

16. The SoC of claim 15, wherein the memory controller is further to:

receive, from the application, a memory store request to store data in the first portion of the contiguous memory block of the memory object of the memory, wherein the memory store request comprises a first pointer indicating a first location of the first portion of the memory block to store the data;

retrieve, from the MCD table, the write protection indicator that indicates the first protection mode of the first portion; and

send, to the application, a fault message when a fault event associated with the first portion occurs based on the first protection mode of the first portion.

17. The SoC of claim 15, wherein the contiguous memory block comprises the first portion of the contiguous memory block and a second portion of the contiguous memory block, wherein:

the first protection mode of the first portion is a write protection mode; and

a second protection mode of the second portion is a non-write protection mode.

18. The SoC of claim 15, wherein the first portion stores at least one of allocation metadata, linked-list pointers, or a return address of a function for a stack.

19. The SoC of claim 15, wherein the MCD metadata word comprises a first byte and a second byte, and wherein:

the first byte comprises;

a MCD unique ID, a mode indicator of the second byte, and a reserved bit; and

the second byte comprises byte level granularity detection information and the write protection indicator.

20. The SoC of claim 15, wherein the contiguous memory block is 64 bytes in size.