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Split voltage non-volatile latch cell

  • US 9,620,225 B2
  • Filed: 09/18/2015
  • Issued: 04/11/2017
  • Est. Priority Date: 01/23/2015
  • Status: Active Grant
First Claim
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1. A memory comprising:

  • an array of non-volatile latch (NVL) cells, each NVL cell comprising;

    a non-volatile portion including;

    a first non-volatile memory (NVM) device and a first pass gate transistor coupled in series between a first output node and a bitline true; and

    a second NVM device and a second pass gate transistor coupled in series between a second output node and a bitline complement; and

    a volatile portion including cross-coupled first and second field effect transistors (FET), the first FET coupled between a supply voltage and the first output node, and the second FET coupled supply voltage and the second output node,wherein a gate of the first FET is coupled to the second output node and a gate of the second FET is coupled to the first output node,wherein the first FET and the second FET are in a same deep well of a first type disposed in a substrate of a second type,wherein each of the first NVM device and the second NVM device is in a well of the second type disposed in the deep well, andwherein the first and second pass gate transistors are respectively configured to isolate the first and second NVM devices from the first and second output nodes when a negative voltage is applied to gates of the first and second pass gate transistors.

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