Split voltage non-volatile latch cell

• US 9,620,225 B2
• Filed: 09/18/2015
• Issued: 04/11/2017
• Est. Priority Date: 01/23/2015
• Status: Active Grant

• Current Assignee: Longitude Flash Memory Solutions, Ltd. (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Ashokkumar, Jayant, Raghavan, Vijay, Prabhakar, Venkatraman, Saha, Swatilekha
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Chen, Xiaochun L
• Application Number:
  US14/858,813
• Publication Number:
  US 20160217861A1
• Time in Patent Office: 571 Days
• Field of Search: 36518508
• CPC Class Codes: G11C 11/2275 Writing or programming circuits or methods
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
• CPC Class Codes: G11C 14/0072 and the nonvolatile element is a ferroelectric element
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits

Abstract

A memory including an array of non-volatile latch (NVL) cells and method of operating the same are provided. In one embodiment, each NVL cell includes a non-volatile portion and a volatile portion. The non-volatile portion includes a first non-volatile memory (NVM) device and a first pass gate transistor coupled in series between a first output node and a bitline true, and a second NVM device and a second pass gate transistor coupled in series between a second output node and a bitline complement. The volatile portion includes cross-coupled first and second field effect transistors (FET), the first FET coupled between a supply voltage (VPWR) and the first output node, and the second FET coupled between VPWR and the second output node. A gate of the first FET is coupled to the second output node, and a gate of the second FET is coupled to the first output node.

Claims

1. A memory comprising:

an array of non-volatile latch (NVL) cells, each NVL cell comprising;

a non-volatile portion including;

a first non-volatile memory (NVM) device and a first pass gate transistor coupled in series between a first output node and a bitline true; and

a second NVM device and a second pass gate transistor coupled in series between a second output node and a bitline complement; and

a volatile portion including cross-coupled first and second field effect transistors (FET), the first FET coupled between a supply voltage and the first output node, and the second FET coupled supply voltage and the second output node,

wherein a gate of the first FET is coupled to the second output node and a gate of the second FET is coupled to the first output node,

wherein the first FET and the second FET are in a same deep well of a first type disposed in a substrate of a second type,

wherein each of the first NVM device and the second NVM device is in a well of the second type disposed in the deep well, and

wherein the first and second pass gate transistors are respectively configured to isolate the first and second NVM devices from the first and second output nodes when a negative voltage is applied to gates of the first and second pass gate transistors.

2. The memory of claim 1, wherein each of the first NVM device and the second NVM device is in a triple well.

3. The memory of claim 2, wherein gates of the first and second NVM devices and the triple wells are biased separately from the negative voltage source (VNEG) and a positive voltage source (VPOS) during erase and program operations to enable split voltage operation to program and erase the first and second NVM devices.

4. The memory of claim 3, further comprising low voltage (LV) devices coupled to the first and second output nodes, wherein the first and second pass gate transistors are configured to isolate the volatile portion of the NVL cell from the split voltage used to erase and program the non-volatile portion during erase and program operations.

5. The memory of claim 3, further comprising high voltage (HV) buffers coupled to the first and second output nodes.

6. The memory of claim 1, wherein the first NVM device and the second NVM device comprise transistors having channels of the same type.

7. The memory of claim 6, wherein the first and second pass gate transistors comprise channels of the same type as the first and second NVM devices, and wherein the first and second FETs comprise channels of a different type from the first and second NVM devices.

8. The memory of claim 7, wherein the first FET and the second FET are in a same deep Nwell of a P-type substrate, and wherein each of the first NVM device and the second NVM device is in a Pwell disposed in the deep Nwell.

9. The memory of claim 1, wherein the first NVM device and the second NVM device comprise silicon-oxide-nitride-oxide-silicon (SONOS), floating gate or FeRAM type NVM devices.

10. The memory of claim 1, wherein the first FET and the second FET are P-channel FETs in a deep Nwell in a P-type substrate, and the first NVM device and the second NVM device comprise N-channel silicon-oxide-nitride-oxide-silicon (SONOS) devices in separate Pwells in the deep Nwell.

11. The memory of claim 10, further comprising an array of flash cells, and a single charge pump integrally formed on a substrate with the array of NVL cells, wherein the charge pump is configured to be used to program and erase both the flash cells and the NVL cells.

12. The memory of claim 1, wherein the first and second field effect FETs comprise weak P-channel metal-oxide-semiconductors (PMOS) transistors having threshold voltages of higher magnitude than the first and second pass gate transistors.

13. A memory comprising:

an array of flash cells;

an array of non-volatile latch (NVL) cells, each NVL cell comprising;

a non-volatile portion including;

a series connected first non-volatile memory (NVM) device and a first pass gate transistor coupled between a first output node and a bitline true, the first pass gate transistor configured to isolate the first NVM device from the first output node when a negative voltage is applied to a gate of the first pass gate transistor; and

a series connected second NVM device and a second pass gate transistor coupled between a second output node and a bitline complement, the second pass gate transistor configured to isolate the second NVM device from the second output node when the negative voltage is applied to a gate of the second pass gate transistor;

a volatile portion including cross-coupled first and second field effect transistors (FET), the first FET coupled between a supply voltage and the first output node, and the second FET coupled between the supply voltage and the second output node, wherein the first FET and the second FET are in a same deep well of a first type disposed in a substrate of a second type, and wherein each of the first NVM device and the second NVM device is in a well of the second type disposed in the deep well; and

a single charge pump configured to be used to program and erase both the flash cells and the NVL cells.

14. The memory of claim 13, wherein each of the first NVM device and second NVM device is in a triple well.

15. The memory of claim 14, wherein gates of the first and the second NVM devices and the triple wells are biased separately from the negative voltage source (VNEG) and a positive voltage source (VPOS) during erase and program operations to enable split voltage operation to program and erase the first and second NVM devices.

16. The memory of claim 14, wherein the first and second pass gate transistors and the first and second NVM devices comprise transistors having channels of the same type, and wherein the first and second FETs comprise channels of a different type.

17. The memory of claim 16, wherein the first FET and the second FET are in a same deep Nwell of a P-type substrate, and wherein each of the first NVM device and the second NVM device is in a Pwell disposed in the deep Nwell.

18. The memory of claim 14, wherein the first FET and the second FET are P-channel FETs in a deep Nwell in a P-type substrate, and the first NVM device and the second NVM device comprise N-channel devices in separate Pwells in the deep Nwell.

19. The NVL cell of claim 18, wherein the first FET and the second FET are weak P-channel FETs having threshold voltages of higher magnitude than the first and second pass gate transistors.

20. A method of programming an array of non-volatile latch (NVL) cells comprising:

providing an array of NVL cells, each including a first non-volatile memory (NVM) device and a first pass gate transistor formed in a PWELL of a triple well and coupled in series between a first output node and a bitline true, a second NVM device and a second pass gate transistor formed in the PWELL and coupled in series between a second output node and a bitline complement, and a volatile latch including cross-coupled first and second field effect transistors coupled between a supply voltage and the output nodes;

isolating the first and second NVM devices in all NVL cells in the array from the output nodes by applying a negative voltage (VNEG) to gates of the first and second pass gate transistors;

applying VNEG to the PWELLs in all NVL cells in the array;

applying VNEG to the bitline true while applying an inhibit voltage (VINH) to the bitline complement in all NVL cells in the array; and

applying a programming voltage (VPOS) to gates of the first and second NVM devices in NVL cells in a selected row of the array while applying VNEG to the first and second NVM devices in NVL cells in a deselected row,

wherein a difference between VPOS and VNEG raises a threshold voltage (V_TP) of the first NVM devices in NVL cells on the selected row, and the difference between VPOS and VNEG applied to the bitline true is sufficient to program first NVM device in NVL cells on the selected row, and wherein the difference between VPOS and VINH applied to the bitline complement is sufficient to inhibit the second NVM devices in NVL cells on the selected row from getting programmed.