Method for fabricating semiconductor device to integrate transistor with passive device

• US 9,620,369 B2
• Filed: 12/11/2013
• Issued: 04/11/2017
• Est. Priority Date: 10/06/2011
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Chen, Chieh-Te, Tzou, Shih-Fang, Liao, Jiunn-Hsiung, Lin, Yi-Po
• Primary Examiner(s): Tran, Long K
• Assistant Examiner(s): Vuong, Thai T
• Application Number:
  US14/103,827
• Publication Number:
  US 20140099760A1
• Time in Patent Office: 1,217 Days
• Field of Search: 257379, 257E27071, 257E21616, 438238
• CPC Class Codes: H01L 21/027 Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 photographic masks or originals per se G03F1/00; registration or positioning of photographic masks or originals G03F9/00; photographic cameras G03B; control of position G05D3/00
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/8232 Field-effect technology
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors

Abstract

A method for fabricating a semiconductor device, wherein the method comprises steps as follows: A dummy gate with a poly-silicon gate electrode and a passive device having a poly-silicon element layer are firstly provided. A hard mask layer is then formed on the dummy gate and the passive device. Next, a first etching process is performed to remove a portion of the hard mask layer to expose a portion of the poly-silicon element layer. Subsequently, an inner layer dielectric (ILD) is formed on the dummy gate and the poly-silicon element layer, and the ILD is flattened by using the hard mask layer as a polishing stop layer. Thereafter, a second etching process is performed to remove the poly-silicon gate electrode, and a metal gate electrode is formed on the location where the poly-silicon gate electrode was initially disposed.

Claims

1. A method for fabricating a semiconductor device comprising:

providing a dummy gate with a poly-silicon gate electrode and a passive device having a poly-silicon element layer, wherein a top surface of the poly-silicon gate electrode and a top surface of the poly-silicon element layer are coplanar;

forming a first spacer on sidewalls of two opposite sides of the dummy gate;

forming a second spacer on sidewalls of two opposite sides of the passive device;

after forming the first spacer and the second spacer, forming a hard mask layer conformally on the first spacer, the second spacer, the dummy gate and the passive device;

performing a first etching process to remove a portion of the hard mask layer and a portion of the poly-silicon element layer to form a recess in the passive device exposing a remaining portion of the poly-silicon element layer;

forming an inner layer dielectric (ILD) on the dummy gate and the poly-silicon element layer;

flattening the ILD by using the hard mask layer as a polish stop layer;

performing a second etching process to remove the poly-silicon gate electrode; and

forming a metal gate electrode on the location where the poly-silicon gate electrode was initially disposed.

2. The method for fabricating the semiconductor device according to claim 1, wherein the formation of the dummy gate and the passive device comprises:

providing a dielectric material layer and a poly-silicon layer stacked in sequence on a substrate; and

patterning the dielectric material layer and the poly-silicon layer to form the poly-silicon gate electrode and the poly-silicon element layer on the patterned dielectric material layer.

3. The method for fabricating the semiconductor device according to claim 2, wherein the dielectric material layer comprises an interfacial layer (IL) and a high-k dielectric layer stacked in sequence on the substrate.

4. The method for fabricating the semiconductor device according to claim 3, further comprising steps of forming a capping layer disposed between the metal gate electrode and high-k dielectric layer.

5. The method for fabricating the semiconductor device according to claim 4, further comprising steps of forming a working function layer on the capping layer, prior to the formation of the metal gate electrode.

6. The method for fabricating the semiconductor device according to claim 2, further comprising steps of forming a source/drain structure by using the dummy gate as a mask, before the second etching process is carried out.

7. The method for fabricating the semiconductor device according to claim 2, prior to the formation of the metal gate electrode, further comprising:

forming a high-k dielectric layer on the location where the poly-silicon gate electrode was initially disposed; and

forming at least one working function layer on the high-k dielectric layer.

8. The method for fabricating the semiconductor device according to claim 1, wherein the second etching process comprises a wet etching and a dry etching.

9. The method for fabricating the semiconductor device according to claim 1, wherein the steps of flattening the ILD comprise a chemical mechanism polishing (CMP) process.