Method for fabricating semiconductor device to integrate transistor with passive device
First Claim
1. A method for fabricating a semiconductor device comprising:
- providing a dummy gate with a poly-silicon gate electrode and a passive device having a poly-silicon element layer, wherein a top surface of the poly-silicon gate electrode and a top surface of the poly-silicon element layer are coplanar;
forming a first spacer on sidewalls of two opposite sides of the dummy gate;
forming a second spacer on sidewalls of two opposite sides of the passive device;
after forming the first spacer and the second spacer, forming a hard mask layer conformally on the first spacer, the second spacer, the dummy gate and the passive device;
performing a first etching process to remove a portion of the hard mask layer and a portion of the poly-silicon element layer to form a recess in the passive device exposing a remaining portion of the poly-silicon element layer;
forming an inner layer dielectric (ILD) on the dummy gate and the poly-silicon element layer;
flattening the ILD by using the hard mask layer as a polish stop layer;
performing a second etching process to remove the poly-silicon gate electrode; and
forming a metal gate electrode on the location where the poly-silicon gate electrode was initially disposed.
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Abstract
A method for fabricating a semiconductor device, wherein the method comprises steps as follows: A dummy gate with a poly-silicon gate electrode and a passive device having a poly-silicon element layer are firstly provided. A hard mask layer is then formed on the dummy gate and the passive device. Next, a first etching process is performed to remove a portion of the hard mask layer to expose a portion of the poly-silicon element layer. Subsequently, an inner layer dielectric (ILD) is formed on the dummy gate and the poly-silicon element layer, and the ILD is flattened by using the hard mask layer as a polishing stop layer. Thereafter, a second etching process is performed to remove the poly-silicon gate electrode, and a metal gate electrode is formed on the location where the poly-silicon gate electrode was initially disposed.
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Citations
9 Claims
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1. A method for fabricating a semiconductor device comprising:
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providing a dummy gate with a poly-silicon gate electrode and a passive device having a poly-silicon element layer, wherein a top surface of the poly-silicon gate electrode and a top surface of the poly-silicon element layer are coplanar; forming a first spacer on sidewalls of two opposite sides of the dummy gate; forming a second spacer on sidewalls of two opposite sides of the passive device; after forming the first spacer and the second spacer, forming a hard mask layer conformally on the first spacer, the second spacer, the dummy gate and the passive device; performing a first etching process to remove a portion of the hard mask layer and a portion of the poly-silicon element layer to form a recess in the passive device exposing a remaining portion of the poly-silicon element layer; forming an inner layer dielectric (ILD) on the dummy gate and the poly-silicon element layer; flattening the ILD by using the hard mask layer as a polish stop layer; performing a second etching process to remove the poly-silicon gate electrode; and forming a metal gate electrode on the location where the poly-silicon gate electrode was initially disposed. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification