Methods of annealing after deposition of gate layers

• US 9,620,386 B2
• Filed: 07/28/2014
• Issued: 04/11/2017
• Est. Priority Date: 07/15/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tsai, Chun Hsiung, Yu, Xiong-Fei, Huang, Yu-Lien, Lin, Da-Wen
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): Newton, Valerie N
• Application Number:
  US14/444,706
• Publication Number:
  US 20140335685A1
• Time in Patent Office: 988 Days
• Field of Search: 438926, 438652-653
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28176 with a treatment, e.g. annealing, after the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A method of fabricating a gate structure includes depositing a high dielectric constant (high-k) dielectric layer over a substrate. The method further includes performing a multi-stage preheat high-temperature anneal. Performing the multi-stage preheat high-temperature anneal includes performing a first stage preheat at a temperature in a range from about 400° C. to about 600° C., performing a second stage preheat at a temperature in a range from about 700° C. to about 900° C., and performing a high temperature anneal at a peak temperature in a range from 875° C. to about 1200° C.

Claims

1. A method of fabricating a gate structure, the method comprising:

depositing a high dielectric constant (high-k) dielectric layer over a substrate; and

performing a multi-stage preheat high-temperature anneal, wherein performing the multi-stage preheat high-temperature anneal comprises;

performing a first stage preheat at a temperature in a range from about 400°

C. to about 600°

C.,

performing a second stage preheat at a temperature in a range from about 700°

C. to about 900°

C., and

performing a high temperature anneal at a peak temperature in a range from 875°

C. to about 1200°

C.

2. The method of claim 1, wherein performing the high temperature anneal comprises performing a millisecond anneal for a duration in a range of about 1 millisecond (ms) to about 40 ms.

3. The method of claim 1, wherein performing the high temperature anneal comprises performing a spike anneal process.

4. The method of claim 3, wherein performing the spike anneal process comprises maintaining the substrate at a temperature within 50-degrees of the peak temperature for a duration ranging from about 0.5 seconds to about 5 seconds.

5. The method of claim 1, further comprising forming an interfacial layer between the substrate and the high-k dielectric layer, wherein performing the multi-stage preheat high-temperature anneal comprises reducing a number of interfacial traps at an interface between the substrate and the interfacial layer.

6. The method of claim 1, further comprising forming a gate electrode over the high-k dielectric layer, wherein forming the gate electrode comprises:

forming a workfunction layer over the high-k dielectric layer;

forming a barrier layer over the workfunction layer; and

forming a metal gate electrode layer over the barrier layer.

7. The method of claim 6, wherein the multi-stage preheat high-temperature anneal is performed prior to forming the metal gate electrode layer.

8. The method of claim 6, further comprising performing a chemical mechanical planarization (CMP) process to remove excess material of the workfunction layer, the barrier layer and the metal gate electrode layer.

9. The method of claim 8, wherein the multi-stage preheat high-temperature anneal is performed after the CMP process.

10. A method of fabricating a gate structure, the method comprising:

forming a high dielectric constant (high-k) dielectric layer over a substrate; and

performing a multi-stage preheat millisecond anneal, wherein performing the multi-stage preheat millisecond anneal comprises;

performing a first stage preheat at a temperature in a range from about 400°

C. to about 600°

C. for a duration in a range from about 2 seconds to about 20 seconds,

performing a second stage preheat at a temperature in a range from about 700°

C. to about 900°

C. for a duration in a range from about 1 second to about 20 seconds, and

performing a millisecond anneal at a peak temperature in a range from 950°

C. to about 1200°

C. for a duration in a range from about 1 millisecond (ms) to about 40 ms.

11. The method of claim 10, further comprising forming an interfacial layer between the substrate and the high-k dielectric layer, wherein performing the multi-stage preheat millisecond anneal comprises reducing a number of interfacial traps at an interface between the substrate and the interfacial layer.

12. The method of claim 10, further comprising forming a gate electrode over the high-k dielectric layer, wherein forming the gate electrode comprises:

forming a workfunction layer over the high-k dielectric layer;

forming a barrier layer over the workfunction layer; and

forming a metal gate electrode layer over the barrier layer.

13. The method of claim 12, wherein the multi-stage preheat millisecond anneal is performed after forming the barrier layer and prior to forming the metal gate electrode layer.

14. The method of claim 12, further comprising performing a chemical mechanical planarization (CMP) process to remove excess material of the workfunction layer, the barrier layer and the metal gate electrode layer.

15. The method of claim 14, wherein the multi-stage preheat millisecond anneal is performed after the CMP process.

16. The method of claim 10, wherein performing the second stage preheat comprises performing a first portion of the second stage preheat prior to the millisecond anneal, and performing a second portion of the second stage preheat after the millisecond anneal.

17. The method of claim 16, wherein performing the first portion of the second stage preheat comprises performing the first portion of the second stage preheat at a first temperature, and performing the second portion of the second stage preheat comprises performing the second portion of the second stage preheat at a second temperature higher than the first temperature.

18. A method of fabricating a gate structure on a wafer, the method comprising:

forming a high dielectric constant (high-k) dielectric layer over a substrate; and

performing a multi-stage preheat millisecond anneal, wherein performing the multi-stage preheat millisecond anneal comprises;

preheating the wafer at a first temperature in a range from about 400°

C. to about 600°

C. for a duration in a range from about 2 seconds to about 20 seconds,

preheating the wafer at a second temperature range from about 700°

C. to about 900°

C. for a duration in a range from about 1 second to about 20 seconds, and

annealing the wafer using a millisecond anneal a peak temperature in a range from 950°

C. to about 1200°

C. for a duration in a range from about 1 ms to about 40 ms, wherein annealing the wafer comprises annealing the wafer at a mid-point of the duration of preheating the wafer at the second temperature.

19. The method of claim 18, wherein preheating the wafer at the second temperature range comprises preheating the wafer for a first duration at a first temperature prior to the millisecond anneal, and preheating the wafer for a second duration at a second temperature after the millisecond anneal, wherein the first temperature is less than the second temperature.

20. The method of claim 18, further comprising:

forming a workfunction layer over the high-k dielectric layer; and

forming a metal gate electrode layer over the workfunction layer, wherein the multi-stage preheat millisecond anneal is performed after forming the workfunction layer and prior to forming the metal gate electrode.