Mechanisms for forming post-passivation interconnect structure

• US 9,620,469 B2
• Filed: 11/18/2013
• Issued: 04/11/2017
• Est. Priority Date: 11/18/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Ying-Ju, Chen, Hsien-Wei
• Primary Examiner(s): Nguyen, Khiem D
• Assistant Examiner(s): Vu, Pauline
• Application Number:
  US14/082,997
• Publication Number:
  US 20150137352A1
• Time in Patent Office: 1,240 Days
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02331 Multilayer structure
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02381 Side view
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03452 Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/03462 Electroplating
• CPC Class Codes: H01L 2224/03464 Electroless plating
• CPC Class Codes: H01L 2224/0347 using a lift-off mask
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05186 with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05583 Three-layer coating
• CPC Class Codes: H01L 2224/05655 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05681 : Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05686 : with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/11 : Manufacturing methods
• CPC Class Codes: H01L 2224/11334 : using preformed bumps
• CPC Class Codes: H01L 2224/11826 : Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/1191 : Forming a passivation layer after forming the bump connector
• CPC Class Codes: H01L 2224/11912 : the bump being used as a mask for patterning other parts
• CPC Class Codes: H01L 2224/13022 : the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13024 : the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13113 : Bismuth [Bi] as principal constituent
• CPC Class Codes: H01L 2224/13116 : Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13561 : On the entire surface of the core, i.e. integral coating
• CPC Class Codes: H01L 2224/1357 : Single coating layer
• CPC Class Codes: H01L 2224/13611 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13613 : Bismuth [Bi] as principal constituent
• CPC Class Codes: H01L 2224/13616 : Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13639 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13647 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13655 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13681 : Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/13686 : with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3157 : Partial encapsulation or coating mask layer used as insulation layer H01L21/31
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 23/53238 : Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01026 : Iron [Fe]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a contact pad over a substrate. The semiconductor device also includes a passivation layer over the substrate and a first portion of the contact pad, and a second portion of the contact pad is exposed through an opening. The semiconductor device further includes a post-passivation interconnect layer over the passivation layer and coupled to the second portion of the contact pad. In addition, the semiconductor device includes a bump over the post-passivation interconnect layer and outside of the opening. The semiconductor device also includes a diffusion barrier layer physically insulating the bump from the post-passivation interconnect layer while electrically connecting the bump to the post-passivation interconnect layer.

Claims

1. A semiconductor device, comprising:

a contact pad over a substrate;

a passivation layer over the substrate and a first portion of the contact pad, wherein a second portion of the contact pad is exposed through an opening;

a post-passivation interconnect layer over the passivation layer and coupled to the second portion of the contact pad; and

a bump over the post-passivation interconnect layer and outside of the opening, wherein the bump has an inner portion and a diffusion barrier region enclosing an entirety of the inner portion, the diffusion barrier region physically insulates the inner portion of the bump from the post-passivation interconnect layer while electrically connecting the inner portion of the bump to the post-passivation interconnect layer, the inner portion of the bump is made of a metal material, and the diffusion barrier region of the bump is made of the metal material doped with a dopant.

2. The semiconductor device as claimed in claim 1, wherein the dopant in the diffusion barrier region includes nickel.

3. The semiconductor device as claimed in claim 1, wherein the metal material includes a solder material or copper.

4. The semiconductor device as claimed in claim 1, wherein a portion of the diffusion barrier region is between a bottom of the inner portion of the bump and the post-passivation interconnect layer.

5. The semiconductor device as claimed in claim 4, further comprising a diffusion barrier layer directly below the diffusion barrier region of the bump and directly above the post-passivation interconnect layer.

6. The semiconductor device as claimed in claim 1, wherein the bump comprises a solder bump.

7. The semiconductor device as claimed in claim 1, wherein the bump comprises copper or copper alloys.

8. The semiconductor device as claimed in claim 1, wherein the post-passivation interconnect layer has a thickness that ranges from about 1/100 to about ⅕

of the diameter of the bump.

17. The semiconductor device as claimed in claim 1, further comprising a molding compound layer covering a rest of the post-passivation interconnect layer that is not covered by the bump, and the molding compound layer is spaced apart from the inner portion of the bump by the diffusion barrier region of the bump.

20. The semiconductor device as claimed in claim 17, wherein a bottom surface of the inner portion of the bump is between a top surface of the molding compound layer and a top surface of the post-passivation interconnect layer.

9. A semiconductor device, comprising:

a contact pad over a semiconductor substrate;

a passivation layer over the semiconductor substrate and a first portion of the contact pad, wherein a second portion of the contact pad is exposed through an opening;

a post-passivation interconnect layer over the passivation layer and coupled to the second portion of the contact pad, wherein the post-passivation interconnect layer comprises copper;

a bump over the post-passivation interconnect layer and outside of the opening, wherein the bump has an inner portion and a diffusion barrier region enclosing an entirety of the inner portion, the diffusion barrier region physically insulates the inner portion of the bump from the post-passivation interconnect layer, the inner portion of the bump is made of a metal material, and the diffusion barrier region of the bump is made of the metal material doped with a dopant.

10. The semiconductor device as claimed in claim 9, wherein the diffusion barrier region of the bump is in direct contact with the post-passivation interconnect layer and electrically connecting the inner portion of the bump to the post-passivation interconnect layer.

18. The semiconductor device as claimed in claim 9, further comprising a molding compound layer covering a rest of the post-passivation interconnect layer that is not covered by the bump, and the molding compound layer is spaced apart from the inner portion of the bump by the diffusion barrier region of the bump.

11. A method for forming a semiconductor device, comprising:

forming a contact pad over a substrate;

forming a passivation layer over the substrate and a first portion of the contact pad while leaving a second portion of the contact pad exposed through an opening;

forming a post-passivation interconnect layer over the passivation layer, wherein the post-passivation interconnect layer is coupled to the second portion of the contact pad; and

forming a bump over the post-passivation interconnect layer, wherein the bump is outside of the opening and electrically connected to the post-passivation interconnect layer, the bump has an inner portion and a diffusion barrier region enclosing an entirety of the inner portion, the diffusion barrier region physically insulates the inner portion of the bump from the post-passivation interconnect layer, the inner portion of the bump is made of a metal material, and the diffusion barrier region of the bump is made of the metal material doped with a dopant.

12. The method as claimed in claim 11, further comprising:

depositing a diffusion barrier layer over the passivation layer; and

placing the bump onto the diffusion barrier layer.

13. The method as claimed in claim 12, further comprising patterning the diffusion barrier layer by using the bump as a mask.

14. The method as claimed in claim 11, wherein the diffusion barrier region is formed by performing an implantation process on the bump to implant the dopant into a region of the bump that encloses an entirety of the inner portion of the bump.

15. The method as claimed in claim 14, further comprising forming a diffusion barrier layer on the post-passivation interconnect layer before the bump are formed over the post-passivation interconnect layer.

16. The method as claimed in claim 14, wherein the implantation process is performed to form the diffusion barrier region before the bump is placed onto the post-passivation interconnect layer.

19. The method as claimed in claim 11, further comprising forming molding compound layer covering a rest of the post-passivation interconnect layer that is not covered by the bump, wherein the molding compound layer is spaced apart from the inner portion of the bump by the diffusion barrier region of the bump.