Method of fabricating a micro device transfer head

• US 9,620,478 B2
• Filed: 02/13/2012
• Issued: 04/11/2017
• Est. Priority Date: 11/18/2011
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Bibl, Andreas, Higginson, John A., Law, Hung-Fai Stephen, Hu, Hsin-Hua
• Primary Examiner(s): Green, Telly
• Application Number:
  US13/372,292
• Publication Number:
  US 20130130416A1
• Time in Patent Office: 1,884 Days
• Field of Search: 156571, 228 495, 438 21
• CPC Class Codes: B32B 2457/20 Displays, e.g. liquid crystal displays, plasma displays
• CPC Class Codes: B32B 37/025 Transfer laminating
• CPC Class Codes: B32B 37/06 characterised by the heating method
• CPC Class Codes: H01L 21/67144 Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
• CPC Class Codes: H01L 21/6833 Details of electrostatic chucks
• CPC Class Codes: H01L 2224/75725 in the upper part of the bonding apparatus, e.g. in the bonding head
• CPC Class Codes: H01L 2224/7598 specially adapted for batch processes
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/83005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/95136 involving guiding structures, e.g. shape matching, spacers or supporting members
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/75 Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 24/95 at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/10329 Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/1421 RF devices
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: Y10T 156/1153 : Temperature change for delamination [e.g., heating during delaminating, etc.]
• CPC Class Codes: Y10T 156/1707 : Discrete spaced laminae on adhered carrier
• CPC Class Codes: Y10T 156/1744 : Means bringing discrete articles into assembled relationship
• CPC Class Codes: Y10T 156/1749 : All articles from single source only
• CPC Class Codes: Y10T 156/1776 : Means separating articles from bulk source

Abstract

A micro device transfer head and head array are disclosed. In an embodiment, the micro device transfer head includes a base substrate, a mesa structure with sidewalls, an electrode formed over the mesa structure, and a dielectric layer covering the electrode. A voltage can be applied to the micro device transfer head and head array to pick up a micro device from a carrier substrate and release the micro device onto a receiving substrate.

Claims

1. A method of fabricating an array of electrostatic transfer heads comprising:

forming an array of mesa structures on a base substrate, each mesa structure including sidewalls;

forming a passivation layer over the base substrate and the array of mesa structures, wherein forming the passivation over the base substrate and the array of mesa structures comprises a technique selected from the group consisting of conformal deposition of the passivation layer over the base substrate and the array of mesa structures and growing the passivation layer over the base substrate and the array of mesa structures;

forming a separate electrode directly on the passivation layer and over each corresponding mesa structure such that each electrode is electrically insulated from each corresponding mesa structure; and

depositing a dielectric layer over the array of mesa structures and each electrode.

2. The method of claim 1, wherein depositing the dielectric layer comprises atomic layer deposition.

3. The method of claim 1, wherein forming the separate electrodes directly on the passivation and over each corresponding mesa structure comprises forming a pair of electrodes over each corresponding mesa structure, wherein each electrode in each pair of electrodes are electrically insulated from each other, and depositing the dielectric layer over the array of mesa structures and each electrode comprises depositing the dielectric layer over each pair of electrodes.

4. The method of claim 3, further comprising forming a conductive ground plane over the dielectric layer and surrounding each of the mesa structures, wherein the conductive ground plane includes an array of openings surrounding the array of mesa structures, and each mesa structure protrudes through a corresponding opening in the conductive ground plane.

5. The method of claim 1, wherein forming the passivation over the base substrate and the array of mesa structures comprises conformal deposition of the passivation layer over the base substrate and the array of mesa structures.

6. The method of claim 1, wherein forming the passivation over the base substrate and the array of mesa structures comprises growing the passivation layer over the base substrate and the array of mesa structures.

7. The method of claim 1, wherein forming the array of mesa structures comprises etching an oxide layer formed over a semiconductor substrate.

8. The method of claim 1, wherein depositing the dielectric layer comprises depositing multiple dielectric layers.

9. The method of claim 1, wherein the array of mesa structures are integrally formed with the base substrate.

10. The method of claim 1, wherein each electrode comprises a material selected from the group consisting of platinum, titanium, vanadium, chromium, zirconium, niobium, molybdenum, ruthenium, rhodium, hafnium, tantalum, tungsten, rhenium, osmium, iridium and alloys thereof.

11. The method of claim 1, wherein each electrode comprises TiW.

12. The method of claim 1, wherein the dielectric layer comprises a dielectric material selected from the group consisting of Al₂O₃ and Ta₂O₅.

13. A method of fabricating an array of electrostatic transfer heads comprising:

forming an array of mesa structures on a base substrate, each mesa structure including sidewalls;

forming a pair of electrodes over each corresponding mesa structure, wherein the electrodes in each pair of electrodes are electrically insulated from each other; and

depositing a dielectric layer over the array of mesa structures and each electrode;

wherein a top surface of the dielectric layer over each mesa structure corresponds to a contact surface for a corresponding electrostatic transfer head in the array of electrostatic transfer heads.

14. The method of claim 13, further comprising forming a pair of electrode leads, wherein each electrode lead runs from a corresponding electrode over a top surface of the corresponding mesa structure along a sidewall of the corresponding mesa structure.

15. The method of claim 13, wherein the pair of electrodes are separated by 0.5 μ

m or less.

16. The method of claim 13, wherein forming the pair of electrodes over each corresponding mesa structure comprises a lift off technique.

17. The method of claim 13, wherein forming the pair of electrodes over each corresponding mesa structure comprises metal layer deposition and etching of the metal layer.

18. A method of fabricating an array of electrostatic transfer heads comprising:

forming an array of mesa structures on a base substrate, each mesa structure including sidewalls;

forming a separate electrode over each corresponding mesa structure;

depositing a dielectric layer over the array of mesa structures and each electrode; and

forming a conductive ground plane over the dielectric layer and surrounding each of the mesa structures, wherein the conductive ground plane includes an array of openings surrounding the array of mesa structures, and each mesa structure protrudes through a corresponding opening in the conductive ground plane.

19. The method of claim 18, wherein the conductive ground plane has a same or lower melting temperature than the separate electrodes.

20. The method of claim 18, wherein the array of mesa structures are integrally formed with the base substrate.