Power semiconductor device with source trench and termination trench implants

• US 9,620,583 B2
• Filed: 09/16/2015
• Issued: 04/11/2017
• Est. Priority Date: 10/08/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Inventors: Kelkar, Kapil, Henson, Timothy D., Ma, Ling, Bigglestone, Mary, Amali, Adam, Burke, Hugo, Haase, Robert
• Primary Examiner(s): Armand, Marc
• Assistant Examiner(s): SALERNO, SARAH KATE
• Application Number:
  US14/856,241
• Publication Number:
  US 20160104766A1
• Time in Patent Office: 573 Days
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power semiconductor device is disclosed. The power semiconductor device includes a source region in a body region, a gate trench adjacent to the source region, and a source trench electrically coupled to the source region. The source trench includes a source trench conductive filler surrounded by a source trench dielectric liner, and extends into a drift region. The power semiconductor device includes a source trench implant below the source trench and a drain region below the drift region, where the source trench implant has a conductivity type opposite that of the drift region. The power semiconductor device may also include a termination trench adjacent to the source trench, where the termination trench includes a termination trench conductive filler surrounded by a termination trench dielectric liner. The power semiconductor device may also include a termination trench implant below the termination trench.

Claims

1. A power semiconductor device comprising:

a source region in a body region;

a gate trench adjacent to said source region;

a source trench electrically coupled to said source region, said source trench having a source trench conductive filler surrounded by a source trench dielectric liner, said source trench extending into a drift region;

a source trench implant below said source trench, said source trench implant having a conductivity type opposite that of said drift region;

said source trench being electrically insulated from said source trench implant by said source trench dielectric liner;

a drain region below said drift region.

2. The power semiconductor device of claim 1 wherein said source trench implant is configured to substantially reduce an impact ionization at an interface between said source trench dielectric liner and said drift region of said source trench.

3. The power semiconductor device of claim 1 wherein said source trench implant and said drift region form a p-n junction below said source trench.

4. The power semiconductor device of claim 1 wherein said gate trench extends through said body region into said drift region.

5. The power semiconductor device of claim 1 further comprising a termination trench adjacent to said source trench.

6. The power semiconductor device of claim 5 wherein said termination trench includes a termination trench conductive filler surrounded by a termination trench dielectric liner.

7. The power semiconductor device of claim 5 further comprising a termination trench implant below said termination trench.

8. A power semiconductor device comprising:

a source region in a body region;

a gate trench adjacent to said source region;

a source trench electrically coupled to said source region;

a termination trench in said drift region adjacent to said source trench, said termination trench having a termination trench conductive filler surrounded by a termination trench dielectric liner;

a termination trench implant below said termination trench, said termination trench implant having a conductivity type opposite that of said drift region;

said termination trench being electrically insulated from said termination trench implant by said termination trench dielectric liner;

a drain region below said drift region.

9. The power semiconductor device of claim 8 wherein said termination trench implant substantially increases a breakdown voltage of said power semiconductor device.

10. The power semiconductor device of claim 8 further comprising a source trench implant under said source trench.

11. The power semiconductor device of claim 8 wherein said termination trench dielectric liner comprises silicon oxide.

12. The power semiconductor device of claim 8 wherein said drift region comprises silicon.

13. A method of forming a power semiconductor device, said method comprising:

forming a drift region of a first conductivity type;

forming a trench in said drift region;

forming a trench implant of a second conductivity type below said trench;

forming a dielectric liner on a bottom and sidewalls of the trench;

depositing, after forming said trench implant of said second conductivity type below said trench, a conductive filler surrounded by said dielectric liner.

14. The method of claim 13 further comprising forming a source region in a body region over said drift region, said source region electrically coupled to said conductive filler in said trench.

15. The method of claim 14 further comprising forming a gate trench adjacent to said source region and extending through said body region into said drift region.

16. The method of claim 14 further comprising forming a drain region below said drift region.

17. The method of claim 13 wherein said trench is a source trench.

18. The method of claim 17 wherein said trench implant is a source trench implant configured to substantially reduce at an interface between said dielectric liner and said drift region.

19. The method of claim 13 wherein said trench is a termination trench.

20. The method of claim 19 wherein said trench implant is a termination trench implant configured to substantially increase a breakdown voltage of said power semiconductor device.