Nanosheet channel-to-source and drain isolation

• US 9,620,590 B1
• Filed: 09/20/2016
• Issued: 04/11/2017
• Est. Priority Date: 09/20/2016
• Status: Active Grant

• Current Assignee: Tessera (Adeia Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Bergendahl, Marc A., Cheng, Kangguo, Lie, Fee Li, Miller, Eric R., Sporre, John R., Teehan, Sean
• Primary Examiner(s): Menz, Laura
• Application Number:
  US15/270,109
• Time in Patent Office: 203 Days
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H05K 999/99 dummy group

Abstract

A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.

Claims

1. A method of fabricating a nanosheet semiconductor device, the method comprising:

forming nanosheet fins including nanosheet stacks comprising alternating silicon (Si) layers and silicon germanium (SiGe) layers on a substrate;

etching each nanosheet fin to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin;

undercutting the SiGe layers in the nanosheet stacks at the first end and the second end to form divots at the first end and the second end;

depositing a dielectric at the first end and the second end, wherein the depositing includes depositing the dielectric in the divots at the first end and the second end;

removing the SiGe layers between the Si layers such that there are gaps between the Si layers of each nanosheet stack and the dielectric anchors the Si layers at the first end and the second end, wherein the removing the SiGe layers precedes forming source and drain regions of the nanosheet semiconductor device;

filling the gaps with an oxide to form second nanosheet stacks comprising alternating layers of the Si and the oxide prior to forming a dummy gate above the nanosheet stacks; and

removing the oxide after removal of the dummy gate and prior to replacement with a replacement gate.

2. The method according to claim 1, further comprising forming a hardmask on each of the nanosheet stacks.

3. The method according to claim 2, further comprising removing the hardmask prior to the forming the dummy gate.

4. The method according to claim 1, wherein the undercutting the SiGe layers includes performing an isotropic etch.

5. The method according to claim 1, wherein the depositing the dielectric includes depositing silicon nitride.

6. The method according to claim 1, wherein the filling the gaps with the oxide includes filling gaps between adjacent second nanosheet stacks along a second axis that is perpendicular to the first axis.

7. The method according to claim 6, further comprising recessing the dielectric and the oxide prior to the forming the dummy gate.

8. The method according to claim 6, further comprising performing a reactive ion etch (RIE) process to remove the oxide between the adjacent second nanosheet stacks prior to the forming the dummy gate.

9. The method according to claim 8, further comprising depositing an extra gate oxide such that the extra gate oxide forms a base for the dummy gate.

10. The method according to claim 6, wherein the filling the gaps includes leaving the dielectric that anchors the Si layers at the first end and the second end.

11. The method according to claim 1, further comprising etching each of the second nanosheets stacks at the first end and the second end to leave second nanosheet stacks only below the dummy gate.

12. The method according to claim 11, further comprising performing an isotropic etch to undercut the oxide in the second nanosheet stacks and form second divots at the first end and the second end.

13. The method according to claim 12, further comprising filling the second divots with an inner spacer.