FinFET gate structure and method for fabricating the same

• US 9,620,610 B1
• Filed: 12/29/2015
• Issued: 04/11/2017
• Est. Priority Date: 10/28/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Jangjian, Shiu-Ko, Hung, Chi-Cheng, Liu, Chi-Wen, Tseng, Horng-Huei
• Primary Examiner(s): Le, Dung
• Application Number:
  US14/983,422
• Publication Number:
  US 20170125537A1
• Time in Patent Office: 469 Days
• Field of Search: 257369, 438156
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device includes a n-type gate structure over a first semiconductor fin, in which the n-type gate structure includes a n-type work function metal layer overlying the first high-k dielectric layer. The n-type work function metal layer includes a TiAl (titanium aluminum) alloy, in which an atom ratio of Ti (titanium) to Al (aluminum) is in a range substantially from 1 to 3. The semiconductor device further includes a p-type gate structure over a second semiconductor fin, in which the p-type gate structure includes a p-type work function metal layer overlying the second high-k dielectric layer. The p-type work function metal layer includes titanium nitride (TiN), in which an atom ratio of Ti to N (nitrogen) is in a range substantially from 1:0.9 to 1:1.1.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a first semiconductor fin on the semiconductor substrate; and

a n-type gate structure over the first semiconductor fin, the n-type gate structure comprising;

a first initial layer over the first semiconductor fin;

a first high-k dielectric layer over the first initial layer and enclosed by a first gate spacer;

a n-type work function metal layer overlying the first high-k dielectric layer, the n-type work function metal layer comprising a TiAl (titanium aluminum) alloy, wherein an atom ratio of Ti (titanium) to Al (aluminum) is in a range substantially from 1 to 3, wherein both surfaces of the n-type work function metal layer contain an oxygen concentration substantially less than 10 atom percent (at %);

a first blocking metal layer overlying the n-type work function metal layer; and

a first metal filler peripherally enclosed by the first blocking metal layer.

2. The semiconductor device of claim 1, wherein the n-type gate structure further comprising:

a capping metal layer between the first high-k dielectric layer and the n-type work function metal layer, wherein the capping metal layer comprises TiN.

3. The semiconductor device of claim 2, the n-type gate structure further comprising:

a barrier metal layer between the capping metal layer and the n-type work function metal layer, the barrier metal layer comprising TaN (tantalum nitride); and

a TiN layer between the barrier metal layer and the n-type work function metal layer.

4. The semiconductor device of claim 1, wherein Al atom concentrations near or at both of the surfaces of the n-type work function metal layer are higher than Al atom concentrations at other portions of the n-type work function metal layer.

5. The semiconductor device of claim 1, further comprising:

a second semiconductor fin on the semiconductor substrate, wherein the first semiconductor fin and the second semiconductor fin are separated by an isolation structure; and

a p-type gate structure over the second semiconductor fin, the p-type gate structure comprising;

a second initial layer over the second semiconductor fin;

a second high-k dielectric layer over the second initial layer and enclosed by a second gate spacer;

a p-type work function metal layer overlying the second high-k dielectric layer, the p-type work function metal layer comprising titanium nitride (TiN), wherein an atom ratio of Ti to N (nitrogen) is in a range substantially from 1;

0.9 to 1;

1.1;

a second blocking metal layer overlying the p-type work function metal layer; and

a second metal filler peripherally enclosed by the second blocking metal layer.

6. The semiconductor device of claim 5, wherein the p-type work function metal layer contains an oxygen concentration substantially less than 10 atom percent (at %).

7. The semiconductor device of claim 5, the p-type gate structure further comprising a TiAl layer disposed between the p-type work function metal layer and the second blocking metal layer.

8. The semiconductor device of claim 5, the p-type gate structure further comprising:

a capping metal layer between the first high-k dielectric layer and the p-type work function metal layer, wherein the capping metal layer comprises TiN.

9. The semiconductor device of claim 8, the p-type gate structure further comprising:

a barrier metal layer between the capping metal layer and the p-type work function metal layer, wherein the barrier metal layer comprises TaN.

10. The semiconductor device of claim 5, wherein each of the first initial layer and the second initial layer comprise a silicon oxide layer.

11. A semiconductor device, comprising:

a semiconductor substrate;

a first semiconductor fin and a second semiconductor fin on the semiconductor substrate, wherein the first semiconductor fin and the second semiconductor fin are separated by an isolation structure; and

a n-type gate structure comprising a first initial layer over the first semiconductor fin and enclosed by a first gate spacer, and a p-type gate structure comprising a second initial layer over the second semiconductor fin and enclosed by a second gate spacer, each of the n-type gate structure and the p-type gate structure comprising;

a high-k dielectric layer over the first initial layer and the second initial layer;

a first TiN layer overlying the high-k dielectric layer;

a TaN layer overlying the first TiN layer;

a second TiN layer overlying the TaN layer;

a TiAl layer overlying the second TiN layer;

a third TiN layer overlying the TiAl layer; and

a metal filler peripherally enclosed by the third TiN layer;

wherein the TiAl layer enclosed by the first gate spacer is a n-type work function metal layer, wherein an atom ratio of Ti (titanium) to Al (aluminum) is in a range substantially from 1 to 3; and

the second TiN layer enclosed by the second gate spacer is a p-type work function metal layer, wherein an atom ratio of Ti to N (nitrogen) is in a range substantially from 1;

0.9 to 1;

1.1.

12. The semiconductor device of claim 11, wherein both surfaces of the n-type work function metal layer contain an oxygen concentration substantially less than 10 atom percent (at %).

13. The semiconductor device of claim 11, wherein the p-type work function metal layer contains an oxygen concentration substantially less than 10 atom percent (at %).

14. The semiconductor device of claim 11, wherein Al atom concentrations near or at both surfaces of the n-type work function metal layer are higher than Al atom concentrations at other portions of the n-type work function metal layer.

15. A method for forming a semiconductor device, the method comprising:

forming a first semiconductor fin and a second semiconductor fin on a semiconductor substrate, wherein the first semiconductor fin and the second semiconductor fin are separated by an isolation structure;

forming a first initial layer enclosed by a first gate spacer over the first semiconductor fin, and a second initial layer enclosed by a second gate spacer over the second semiconductor fin;

forming a high-k dielectric layer over the first initial layer and the second initial layer;

forming a first TiN layer over the high-k dielectric layer;

forming a TaN layer over the first TiN layer;

forming a second TiN layer over the TaN layer;

forming a TiAl layer over the second TiN layer;

forming a third TiN layer over the TiAl layer; and

forming a metal filler peripherally enclosed by the third TiN layer;

wherein the TiAl layer enclosed by the first gate spacer acts as a n-type work function metal layer, wherein an atom ratio of Ti (titanium) to Al (aluminum) is in a range substantially from 1 to 3; and

the second TiN layer enclosed by the second gate spacer acts as a p-type work function metal layer, wherein an atom ratio of Ti to N (nitrogen) is in a range substantially from 1;

0.9 to 1;

1.1.

16. The method of claim 15, wherein operations of forming the first TiN layer, the second TiN layer, the third TiN layer, the TaN layer, the TiAl layer and the metal filler are performed by atomic layer deposition (ALD).

17. The method of claim 15, wherein both surfaces of then-type work function metal layer contain an oxygen concentration substantially less than 10 atom percent (at %), and Al atom concentrations near or at the both surfaces of the n-type work function metal layer are higher than Al atom concentrations at other portions of the n-type work function metal layer.

18. The method of claim 15, wherein the p-type work function metal layer contains an oxygen concentration substantially less than 10 atom percent (at %).

19. The method of claim 15, further comprising:

forming source/drain portions respectively on the first semiconductor fin adjacent to both sides of the first gate spacer, and on the second semiconductor fin adjacent to both sides of the second gate spacer.