Intergrated circuit devices including an interfacial dipole layer

• US 9,620,612 B2
• Filed: 02/19/2015
• Issued: 04/11/2017
• Est. Priority Date: 02/19/2015
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Xu, Jeffrey Junhao, Li, Xia
• Primary Examiner(s): Soward, Ida M
• Application Number:
  US14/625,974
• Publication Number:
  US 20160247893A1
• Time in Patent Office: 782 Days
• CPC Class Codes: G11C 11/221 using ferroelectric capacitors
• CPC Class Codes: H01L 21/02148 the material containing hafnium, e.g. HfSiOx or HfSiON
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/02186 the material containing titanium, e.g. TiO2
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/40111 the electrodes comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66568 Lateral single gate silicon transistors
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/6684 with a ferroelectric gate insulator
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 43/30 : characterised by the memory core region
• CPC Class Codes: H10B 51/40 : characterised by the peripheral circuit region

Abstract

An integrated circuit device includes a first transistor structure formed in a memory region (e.g., an embedded memory region) of a die. The first transistor structure includes a substrate (e.g., a planar substrate of a planar FET or a fin of a FinFET) and a first gate. The first gate includes a dipole layer proximate to the substrate and a barrier layer proximate to the dipole layer. The integrated circuit device further includes a second transistor structure formed in a logic device region of the die. The second transistor structure includes a second gate that includes an interface layer, a dielectric layer, and a cap layer. The dielectric layer is formed between the cap layer and the interface layer.

Claims

1. An integrated circuit device, comprising:

a first transistor structure in a memory region of a die, the first transistor structure having a substrate and a first gate, the first gate including a dipole layer proximate to the substrate and a barrier layer proximate to the dipole layer; and

a second transistor structure in a logic device region of the die, the second transistor structure having a second gate, the second gate including an interface layer, a dielectric layer, and a cap layer, the dielectric layer between the cap layer and the interface layer.

2. The integrated circuit device of claim 1, wherein the barrier layer is on the dipole layer and on the cap layer.

3. The integrated circuit device of claim 1, wherein the dielectric layer includes hafnium oxide (HfO₂), the dipole layer includes hafnium silicon oxide (HfSiO₄), or both.

4. The integrated circuit device of claim 1, wherein the first transistor structure comprises a first field effect transistor (FET), the substrate includes a substrate of the first FET, and the second transistor structure comprises a second FET.

5. The integrated circuit device of claim 4, wherein the interface layer is proximate to a second substrate of the second FET.

6. The integrated circuit device of claim 1, wherein a gate stack of the first gate includes:

a metal layer proximate to the barrier layer;

a second barrier layer proximate to the metal layer; and

a fill metal layer proximate to the second barrier layer.

7. The integrated circuit device of claim 6, wherein a gate stack of the second gate includes:

the interface layer proximate to a second substrate;

the dielectric layer proximate to the interface layer;

the cap layer proximate to the dielectric layer;

the barrier layer proximate to the cap layer;

the metal layer proximate to the barrier layer;

the second barrier layer proximate to the metal layer; and

the fill metal layer proximate to the second barrier layer.

8. An integrated circuit device comprising:

means for storing one or more bits formed in a memory region of a die, the means for storing including a first gate that includes a dipole layer; and

means for performing a logical function formed in a logic device region of the die, the means for performing including a second gate, the second gate including an interface layer, a dielectric layer, and a cap layer, the dielectric layer proximate to the interface layer and between the cap layer and the interface layer.

9. The integrated circuit device of claim 8, wherein a barrier layer is on the dipole layer and on the cap layer.

10. The integrated circuit device of claim 8, wherein the dielectric layer includes hafnium oxide (HfO₂), the dipole layer includes hafnium silicon oxide (HfSiO₄), or both.

11. The integrated circuit device of claim 8, wherein a gate stack of the first gate includes:

a metal layer proximate to a barrier layer;

a second barrier layer proximate to the metal layer; and

a fill metal layer proximate to the second barrier layer.

12. The integrated circuit device of claim 11, wherein a gate stack of the second gate includes:

the interface layer proximate to a second substrate;

the dielectric layer proximate to the interface layer;

the cap layer proximate to the dielectric layer;

the barrier layer proximate to the cap layer;

the metal layer proximate to the barrier layer;

the second barrier layer proximate to the metal layer; and

the fill metal layer proximate to the second barrier layer.