Gate structure of field effect transistor with footing
First Claim
Patent Images
1. A field effect transistor (FET) structure, comprising:
- a substrate having a surface;
a first semiconductor structure comprising;
a channel region, anda source region and a drain region formed on opposite ends of the channel region, respectively; and
a gate structure comprising;
a central region formed over the surface and at least wrapping around three sides of the channel region, and footing regions formed on opposite sides of the central region and along where the central region is adjacent to the first semiconductor structure;
wherein the central region includes a gate dielectric, a work function metal layer and a fill metal;
wherein the gate dielectric and the work function metal layer extend to the footing regions, and the fill metal does not extend to the footing regions.
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Abstract
In some embodiments, an field effect transistor structure includes a first semiconductor structure and a gate structure. The first semiconductor structure includes a channel region, and a source region and a drain region. The source region and the drain region are formed on opposite ends of the channel region, respectively. The gate structure includes a central region and footing regions. The central region is formed over the first semiconductor structure. The footing regions are formed on opposite sides of the central region and along where the central region is adjacent to the first semiconductor structure.
11 Citations
20 Claims
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1. A field effect transistor (FET) structure, comprising:
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a substrate having a surface; a first semiconductor structure comprising; a channel region, and a source region and a drain region formed on opposite ends of the channel region, respectively; and a gate structure comprising; a central region formed over the surface and at least wrapping around three sides of the channel region, and footing regions formed on opposite sides of the central region and along where the central region is adjacent to the first semiconductor structure; wherein the central region includes a gate dielectric, a work function metal layer and a fill metal; wherein the gate dielectric and the work function metal layer extend to the footing regions, and the fill metal does not extend to the footing regions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A semiconductor structure, comprising:
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a first semiconductor structure; and a gate structure comprising; a central region formed over the first semiconductor structure, and footing regions formed on opposite sides of the central region and along where the central region is adjacent to the first semiconductor structure; wherein the central region includes a gate dielectric, a work function metal layer and a fill metal; wherein the gate dielectric and the work function metal layer extend to the footing regions, and the fill metal does not extend to the footing regions. - View Dependent Claims (10, 11, 12, 13)
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14. A semiconductor structure, comprising:
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a first semiconductor structure comprising; a channel region, and a source region and a drain region formed on opposite ends of the channel region, respectively; a gate structure comprising; a gate dielectric; a work function metal layer; and a fill metal; wherein a central region of the gate structure is formed over the first semiconductor structure, and a portion of the gate dielectric and a portion of the work function metal layer form footing regions of the gate structure on opposite sides of the central region and along where the central region is adjacent to the first semiconductor structure, and the fill metal is not included in the footing region, wherein each footing region is tapered towards the central region from a first end of the footing region to a second end of the footing region, and the first end of the footing region is closer to the first semiconductor structure than the second end of the footing region; and an interfacial layer formed between the first semiconductor structure and the gate structure. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification