FinFET with epitaxial source and drain regions and dielectric isolated channel region

• US 9,620,641 B2
• Filed: 02/22/2016
• Issued: 04/11/2017
• Est. Priority Date: 05/01/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Divakaruni, Ramachandra, Khakifirooz, Ali, Reznicek, Alexander, Seo, Soon-Cheon
• Primary Examiner(s): Feliciano, Eliseo Ramos
• Assistant Examiner(s): SINGAL, ANKUSH K
• Application Number:
  US15/049,796
• Publication Number:
  US 20160172498A1
• Time in Patent Office: 414 Days
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure. At least one of the source and drain region structures includes at least two epitaxial material layers. A first epitaxial material layer is in contact with the at least one layer of semiconductor material. A second epitaxial material layer is in contact with the at least one fin structure. The first epitaxial material layer is separated from the at least one fin structure by the second epitaxial material layer. A gate structure present on the at least one fin structure.

Claims

1. A structure comprising:

a pedestal of an insulating material present over at least one layer of a semiconductor material that includes a punch through barrier layer;

at least one fin structure in contact with the pedestal of the insulating material; and

source and drain region structures on opposing sides of the at least one fin structure, at least one of the source and drain region structures comprising at least two epitaxial material layers, wherein a first epitaxial material layer of the at least two epitaxial layers is in contact with the punch through barrier layer of the at least one layer of semiconductor material, and a second epitaxial material layer of the at least two epitaxial layers is in contact with the at least one fin structure, the first epitaxial material layer being separated from the at least one fin structure by the second epitaxial material layer.

2. The structure according to claim 1 further comprising a gate structure present on the at least one fin structure.

3. The structure according to claim 1, wherein the at least one fin structure is a channel region, and an interface between the second epitaxial material layer of the source and drain region structures and the channel region is substantially free of defects.

4. The structure according to claim 1, wherein the at least one layer of semiconductor material further comprises a semiconductor substrate, wherein the punch through barrier layer is present between the pedestal of the insulating material and the semiconductor substrate.

5. The structure according to claim 4, wherein the punch through barrier layer is a doped portion of the substrate.

6. The structure according to claim 4, wherein the punch through barrier layer is doped to a conductivity type that is opposite a conductivity type of the source and drain region structures.

7. The structure according to claim 4, wherein the second epitaxial layer is in contact with the punch through barrier layer.

8. The structure according to claim 2, wherein a gate sidewall spacer is present on the gate structure, wherein a sidewall of the fin structure is aligned with an outer sidewall of the gate sidewall spacer, the first epitaxial material layer having a vertical portion in contact with the sidewall of the fin structure and a horizontal portion on an upper surface of the second epitaxial material layer.

9. The structure according to claim 7, wherein the first epitaxial material layer has a crystalline structure that is aligned with a crystalline structure of the punch-through layer, and the second epitaxial material layer has a crystalline structure that is aligned with a crystal structure of the sidewall of the at least one fin structure.

10. The structure according to claim 1, wherein the structure is a FinFET semiconductor device.