FinFET with isolation

• US 9,620,642 B2
• Filed: 12/11/2013
• Issued: 04/11/2017
• Est. Priority Date: 12/11/2013
• Status: Active Grant

• Current Assignee: Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Inventors: Toh, Eng Huat, Tan, Shyue Seng, Quek, Elgin Kiok Boone
• Primary Examiner(s): Malsawma, Lex
• Assistant Examiner(s): SWAN, GARDNER W.S
• Application Number:
  US14/103,780
• Publication Number:
  US 20150162436A1
• Time in Patent Office: 1,217 Days
• CPC Class Codes: H01L 21/76205 in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
• CPC Class Codes: H01L 2221/1047 the air gaps being formed by pores in the dielectric
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

Devices and methods for forming a device are presented. The method includes providing a substrate prepared with a device region. A fin is formed in the device region. The fin includes top and bottom portions. An isolation layer is formed on the substrate. The isolation layer has a top isolation surface disposed below a top fin surface, leaving an upper fin portion exposed. At least one isolation buffer is formed in the bottom fin portion, leaving the top fin portion crystalline, the top fin portion serves as a body of a fin type transistor. Source/drain (S/D) regions are formed in the top portions of the fin and a gate wrapping around the fin is provided.

Claims

1. A method for forming a device comprising:

providing a substrate prepared with a device region;

forming a fin in the device region, the fin includes top and bottom fin portions, wherein the top fin portion serves as a body of a fin type transistor;

forming an isolation layer on the substrate, wherein the isolation layer has a top isolation surface disposed below the top fin portion;

forming at least one isolation buffer in the bottom fin portion, leaving the top fin portion crystalline, wherein the at least one isolation buffer does not extend throughout the entire length of the bottom fin portion and partially isolates the top fin portion from the substrate, wherein forming the at least one isolation buffer comprises

performing an oxidation process to form at least one oxidized portion in the bottom fin portion,

removing the at least one oxidized portion to form a complete void, and

filling the complete void with an oxide material having a plurality of voids, wherein the at least one isolation buffer is a hybrid isolation buffer;

forming source/drain (S/D) regions in the top portions of the fin; and

forming a gate wrapping around the fin, wherein the gate comprises a top gate portion on top of the fin and side gate portions extending from a top surface of the fin towards the top isolation surface, wherein the side gate portions extend below the S/D regions and are in direct contact with sidewalls of the bottom fin portion.

2. The method of claim 1 wherein forming the isolation layer comprises providing an isolation layer having an initial thickness T₁ and performing an etch to recess the isolation layer from the initial thickness T₁ to a final thickness T₂.

3. The method of claim 2 comprising:

forming protective liners on sidewalls of an upper fin portion over the isolation layer prior to recessing the isolation layer from T₁ to T₂, wherein forming the protective liners include a blanket deposition process to form a protective layer on the fin and isolation layer, and performing an etch to remove horizontal portions of the protective layer, leaving vertical portions of the protective layer to form the protective liners.

4. The method of claim 3 wherein forming the at least one isolation buffer comprises forming first and second isolation buffers which are separated from each other under the S/D regions.

5. The method of claim 4 wherein forming the first and second isolation buffers comprises:

recessing the isolation layer from T₁ to T₂ after forming the protective liners;

doping exposed portions of the fin in-between the protective liners and a top surface of the recessed isolation layer; and

wherein the oxidation process is performed to oxidize the exposed doped fin portions to form first and second oxide portions.

6. The method of claim 5 comprising forming a dummy gate over the substrate prior to performing the oxidation process, wherein the dummy gate protects the bottom fin portion under a channel region below the gate from being oxidized.

7. The method of claim 6 comprising:

performing an etch to remove the first and second oxide portions to form first and second complete voids below the S/D regions; and

filling the complete voids with the oxide material having the plurality of voids to form the first and second isolation buffers.

8. The method of claim 6 comprising:

removing the protective liners after forming the isolation buffers;

forming sidewall spacers on exposed sidewalls of the dummy gate; and

forming raised S/D regions on the S/D regions.

9. The method of claim 8 comprising:

forming an interlevel dielectric (ILD) layer on the substrate covering the fin, dummy gate and isolation layer;

performing a planarization process to form a top ILD surface which is about co-planar with the top surface of the dummy gate; and

removing the dummy gate after the planarization process to form the gate.

10. The method of claim 3 wherein the at least one isolation buffer is disposed under a channel region below the gate.

11. The method of claim 10 comprising:

forming a dummy gate over the substrate prior to forming the gate;

forming sidewall spacers on sidewalls of the dummy gate; and

forming raised S/D regions on the S/D regions after forming the sidewall spacers.

12. The method of claim 11 comprising:

forming an interlevel dielectric (ILD) layer on the substrate covering the fin, dummy gate and isolation layer;

performing a planarization process to form a top ILD surface which is about co-planar with top surface of the dummy gate; and

removing the dummy gate after the planarization process to form a gate trench and expose the sidewall spacers.

13. The method of claim 12 wherein the protective liners are formed in the gate trench over the exposed sidewall spacers and the isolation buffer under the channel region is formed by:

doping an exposed portion of the fin in-between the protective liners and the top isolation surface of the recessed isolation layer; and

wherein the oxidation process is performed to oxidize the exposed doped fin portion to form an oxide portion, wherein the ILD layer protects the bottom fin portion below the S/D regions from being oxidized.

14. The method of claim 13 comprising:

performing an etch to remove the oxide portion to form the complete void below the channel region; and

filling the complete void with the oxide material having the plurality of voids to form the isolation buffer.

15. A method for forming a device comprising:

providing a substrate prepared with a device region;

forming a fin structure in the device region, the fin structure includes top and bottom fin portions, wherein the top fin portion serves as a body of a fin type transistor;

forming an isolation layer on the substrate, wherein the isolation layer has a top isolation surface disposed below the top fin portion;

forming at least one isolation segment in the bottom fin portion and leaving the top fin portion crystalline, wherein forming the at least one isolation segment comprises

performing an oxidation process to form at least one oxidized portion in the bottom fin portion,

removing the at least one oxidized portion to form a complete void, and

filling the complete void with an oxide material having a plurality of voids, wherein the at least one isolation segment is a hybrid isolation segment, the at least one isolation segment partially isolates the top fin portion from the substrate;

forming first and second source/drain (S/D) regions of the fin type transistor, wherein each of the S/D regions include a base S/D portion disposed within the top fin portion and a raised S/D portion disposed on the base S/D portion; and

forming a gate wrapping around the fin structure, wherein the gate comprises a top gate portion on top of the fin and side gate portions extending from a top surface of the fin towards the top isolation surface, wherein the side gate portions extend below the S/D regions and in direct contact with sidewalls of the bottom fin portion.

16. The method of claim 15 wherein the bottom fin portion includes at least one crystalline segment conductively coupling the top fin portion to the substrate.

17. The method of claim 16 wherein the at least one isolation segment comprises first and second isolation segments which are separated from each other, wherein the first and second isolation segments isolate the first and second S/D regions from the substrate while the at least one crystalline segment conductively couples a channel region of the fin type transistor to the substrate.

18. The method of claim 16 wherein the at least one isolation segment isolates a channel region of the fin type transistor from the substrate while the at least one crystalline segment comprises first and second crystalline segments coupling the first and second S/D regions to the substrate.

19. A method for forming a device comprising:

providing a substrate prepared with a device region;

forming a fin in the device region, the fin includes top and bottom portions;

forming a dummy gate over the substrate;

forming an isolation layer on the substrate, wherein the isolation layer has a top isolation surface disposed below the top fin portion, wherein forming the isolation layer comprises providing an isolation layer having an initial thickness T₁ and performing an etch to recess the isolation layer from the initial thickness T₁ to a final thickness T₂;

forming protective liners on sidewalls of an upper fin portion over the isolation layer prior to recessing the isolation layer from T₁ to T₂, wherein forming the protective liners include a blanket deposition process to form a protective layer on the fin and isolation layer, and performing an etch to remove horizontal portions of the protective layer, leaving vertical portions of the protective layer to form the protective liners;

forming at least one isolation buffer in the bottom fin portion, leaving the top fin portion crystalline, wherein the at least one isolation buffer does not extend throughout the entire length of the bottom fin portion and partially isolates the top fin portion from the substrate, the top fin portion serves as a body of a fin type transistor, wherein forming the at least one isolation buffer comprises forming first and second isolation buffers which are separated from each other under the S/D regions, wherein forming the first and second isolation buffers comprises

recessing the isolation layer from T₁ to T₂ after forming the protective liners,

doping exposed portions of the fin in-between the protective liners and a top surface of the recessed isolation layer, and

performing an oxidation process to the exposed doped fin portions to form first and second oxide portions, wherein the dummy gate protects the bottom fin portion under a channel region below the gate from being oxidized;

performing an etch to remove the first and second oxide portions to form first and second complete voids below the S/D regions;

filling the complete voids with an oxide material having a plurality of voids to form the first and second isolation buffers, wherein the isolation buffers are hybrid isolation buffers;

forming source/drain (S/D) regions in the top portions of the fin; and

forming a gate wrapping around the fin, wherein the gate comprises a top gate portion on top of the fin and side gate portions extending from a top surface of the fin towards the top isolation surface, wherein the side gate portions extend below the S/D regions and in direct contact with sidewalls of the bottom fin portion.