Micro device with stabilization post

• US 9,620,695 B2
• Filed: 06/24/2016
• Issued: 04/11/2017
• Est. Priority Date: 07/08/2013
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Hu, Hsin-Hua, Chang, Kevin K. C., Bibl, Andreas
• Primary Examiner(s): Valentine, Jami M
• Application Number:
  US15/192,936
• Publication Number:
  US 20160308103A1
• Time in Patent Office: 291 Days
• Field of Search: 257 13, 439 26
• CPC Class Codes: H01L 2224/83005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 24/75 Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 24/95 at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 27/15 including semiconductor components having potential barriers, specially adapted for light emission
• CPC Class Codes: H01L 27/156 two-dimensional arrays
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2933/0066 relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 33/005 Processes
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/0095 Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/04 with a quantum effect structure or superlattice, e.g. tunnel junction
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/08 with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body H01L27/15 takes precedence
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/60 Reflective elements
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

A method and structure for stabilizing an array of micro devices is disclosed. A stabilization layer includes an array of stabilization cavities and array of stabilization posts. Each stabilization cavity includes sidewalls surrounding a stabilization post. The array of micro devices is on the array of stabilization posts. Each micro device in the array of micro devices includes a bottom surface that is wider than a corresponding stabilization post directly underneath the bottom surface.

Claims

1. A structure comprising:

a stabilization layer comprising an array of stabilization cavities and an array of stabilization posts, wherein each stabilization cavity includes a stabilization post and sidewalls that surround and are taller than the stabilization post; and

an array of chips on the array of stabilization posts;

wherein each chip in the array of chips includes a bottom surface that is wider than a corresponding stabilization post directly underneath the bottom surface, and each chip includes circuitry to control one or more LED devices.

2. The structure of claim 1, wherein the circuitry of each chip is to control more than one LED device.

3. The structure of claim 2, wherein each chip includes an active silicon layer and a build up layer underneath the active silicon layer.

4. The structure of claim 1, further comprising a sacrificial layer between the stabilization layer and the array of chips, wherein the array of stabilization posts extend through a thickness of the sacrificial layer, and wherein the sacrificial layer spans along a side surface of each of the chips in the array of chips, the side surface running between a top surface and the bottom surface of each chip in the array.

5. The structure of claim 4, wherein the sacrificial layer comprises an oxide or nitride.

6. The structure of claim 1, further comprising an array of bottom conductive contacts on the bottom surfaces of the array of chips.

7. The structure of claim 6, wherein each stabilization post includes a top surface contact area that is less than a bottom surface contact area of a corresponding bottom conductive contact.

8. The structure of claim 6, wherein each bottom conductive contact comprises a layer stack.

9. The structure of claim 8, wherein the layer stack comprises:

an electrode layer;

a mirror layer on the electrode layer;

a barrier layer on the mirror layer;

a diffusion barrier layer on the barrier layer; and

a bonding layer on the diffusion barrier layer.

10. The structure of claim 8, wherein the layer stack comprises:

an electrode layer comprising nickel;

a mirror layer comprising silver on the electrode layer;

a barrier layer comprising titanium on the mirror layer;

a diffusion barrier layer comprising platinum on the barrier layer; and

a bonding layer comprising a noble metal on the diffusion barrier layer.

11. The structure of claim 8, wherein the layer stack comprises a bonding layer, and the bonding layer comprises a noble metal.

12. The structure of claim 11, wherein the stabilization layer is formed of a thermoset material.

13. The structure of claim 12, wherein the thermoset material comprises benzocyclobutene (BCB), and the noble metal is gold.

14. The structure of claim 8, wherein the layer stack further comprises:

an electrode layer on the bottom surface of the chip;

a diffusion barrier layer on and around sidewalls the electrode layer; and

a bonding layer on the diffusion barrier layer.

15. The structure of claim 14, wherein the stabilization layer is formed of a thermoset material, and the bonding layer comprises a noble metal.

16. The structure of claim 1, wherein the stabilization posts in the array of stabilization posts are separated by a pitch of 1 μ

m to 100 μ

m.

17. The structure of claim 1, wherein each chip includes a top surface that is above a corresponding staging cavity sidewalls top surface.

18. The structure of claim 1, wherein each chip has a maximum dimension of 1 μ

m to 100 μ

m.