Semiconductor package having an over-temperature protection circuit utilizing multiple temperature threshold values
First Claim
1. A semiconductor package comprising:
- a multi-phase power inverter having power switches and situated on a leadframe of said semiconductor package, said power switches including at least one high side switch and at least one low side switch; and
an over-temperature protection circuit configured to reduce current through said power switches based on multiple temperature threshold values of said power switches and a sensed temperature of said power switches, wherein said over-temperature protection circuit is configured to;
in response to determining that said sensed temperature is greater than a first temperature threshold value of said multiple temperature threshold values and is less than a second temperature threshold value of said multiple temperature threshold values, disable switching of said at least one high side power switch and refrain from disabling switching of said at least one low side power switch; and
in response to determining that said sensed temperature is greater than said second temperature threshold value, periodically disable switching of said at least one high side switch and said at least one low side switch.
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Accused Products
Abstract
According to an exemplary implementation, a semiconductor package includes a multi-phase power inverter having power switches and situated on a leadframe of the semiconductor package. The semiconductor package further includes an over-temperature protection circuit configured to reduce current through the power switches based on multiple temperature threshold values of the power switches and a sensed temperature of the power switches. The over-temperature protection circuit can be configured to enter first and second modes based on the multiple temperature threshold values and the sensed temperature, where the second mode reduces current through the power switches to a greater extent than the first mode.
66 Citations
18 Claims
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1. A semiconductor package comprising:
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a multi-phase power inverter having power switches and situated on a leadframe of said semiconductor package, said power switches including at least one high side switch and at least one low side switch; and an over-temperature protection circuit configured to reduce current through said power switches based on multiple temperature threshold values of said power switches and a sensed temperature of said power switches, wherein said over-temperature protection circuit is configured to; in response to determining that said sensed temperature is greater than a first temperature threshold value of said multiple temperature threshold values and is less than a second temperature threshold value of said multiple temperature threshold values, disable switching of said at least one high side power switch and refrain from disabling switching of said at least one low side power switch; and in response to determining that said sensed temperature is greater than said second temperature threshold value, periodically disable switching of said at least one high side switch and said at least one low side switch. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A semiconductor package comprising:
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a multi-phase power inverter having power switches and situated on a leadframe of said semiconductor package, said power switches including at least one high side switch and at least one low side switch; an over-temperature protection circuit configured to in response to determining that a sensed temperature of said power switches is greater than a first temperature threshold value and is less than a second temperature threshold value, enter a first mode that reduces current through said power switches; and in response to determining that said sensed temperature is greater than said second temperature threshold value and is less than a third temperature threshold value, enter a second mode that reduces current through said power switches; wherein said first mode disables switching of said at least one high side power switch and refrains from disabling switching of said at least one low side power switch; and wherein said second mode periodically disables switching of said at least one high side power switch and said at least one low side switch. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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Specification