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Frequency scaling method, circuit and associated all-digital phase-locked loop

  • US 9,621,171 B1
  • Filed: 09/30/2015
  • Issued: 04/11/2017
  • Est. Priority Date: 09/30/2015
  • Status: Active Grant
First Claim
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1. A frequency scaling method for changing an output frequency of an all-digital phase-locked loop (ADPLL) from a first frequency to a second frequency different from the first frequency, the method comprising:

  • stopping feeding a first oscillator tuning word (OTW) to a digitally controlled oscillator (DCO) of the ADPLL, wherein the first OTW is generated based on a phase detecting result obtained with respect to the first frequency;

    feeding a second OTW to the DCO to change the output frequency from the first frequency to the second frequency; and

    performing a zero phase restart (ZPR) operation to produce a phase detecting result according to the second frequency.

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