Frequency scaling method, circuit and associated all-digital phase-locked loop
First Claim
1. A frequency scaling method for changing an output frequency of an all-digital phase-locked loop (ADPLL) from a first frequency to a second frequency different from the first frequency, the method comprising:
- stopping feeding a first oscillator tuning word (OTW) to a digitally controlled oscillator (DCO) of the ADPLL, wherein the first OTW is generated based on a phase detecting result obtained with respect to the first frequency;
feeding a second OTW to the DCO to change the output frequency from the first frequency to the second frequency; and
performing a zero phase restart (ZPR) operation to produce a phase detecting result according to the second frequency.
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Abstract
A frequency scaling method is disclosed. The method is used for changing an output frequency of an all-digital phase-locked loop (ADPLL) from a first frequency to a second frequency different from the first frequency. The method includes: stopping a feeding of a first oscillator tuning word (OTW) to a digitally controlled oscillator (DCO) of the ADPLL, wherein the first OTW is generated based on a phase detecting result obtained with respect to the first frequency; feeding a second OTW to the DCO in order to change the output frequency from the first frequency to the second frequency; and performing a zero phase restart (ZPR) operation to produce the phase detecting result according to the second frequency. An associated ADPLL and a frequency scaling circuit are also disclosed.
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Citations
20 Claims
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1. A frequency scaling method for changing an output frequency of an all-digital phase-locked loop (ADPLL) from a first frequency to a second frequency different from the first frequency, the method comprising:
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stopping feeding a first oscillator tuning word (OTW) to a digitally controlled oscillator (DCO) of the ADPLL, wherein the first OTW is generated based on a phase detecting result obtained with respect to the first frequency; feeding a second OTW to the DCO to change the output frequency from the first frequency to the second frequency; and performing a zero phase restart (ZPR) operation to produce a phase detecting result according to the second frequency. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An all-digital phase-locked loop (ADPLL), comprising:
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a phase detecting circuit configured to detect a phase difference between an output frequency of a digitally controlled oscillator (DCO) and a reference frequency, and generating a phase detecting result based on the detected phase difference; a DCO coupled to the phase detecting circuit, and the DCO being configured to generate the output frequency responsive to the phase detecting result; and a frequency scaling circuit coupled to the phase detecting circuit and the DCO, and the frequency scaling circuit being configured to selectively feed a first oscillator tuning word (OTW) generated based on the phase detecting result or a second OTW to the DCO, so as to change the output frequency of the DCO from a first frequency to a second frequency. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A frequency scaling circuit for controlling a phase detecting circuit and a digitally controlled oscillator (DCO) in order to change an output frequency from a first frequency to a second frequency, comprising:
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a control pulse generator configured to selectively feed a first oscillator tuning word (OTW) generated based on a phase detecting result by the phase detecting circuit or a second OTW to the DCO; and an OTW injector configured to generate the second OTW. - View Dependent Claims (19, 20)
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Specification