Circuits and methods of implementing time-average-frequency direct period synthesizer on programmable logic chip and driving applications using the same

• US 9,621,173 B1
• Filed: 11/19/2015
• Issued: 04/11/2017
• Est. Priority Date: 11/19/2015
• Status: Active Grant

• Current Assignee: Liming Xiu
• Original Assignee: Liming Xiu
• Inventors: Xiu, Liming
• Primary Examiner(s): Whitmore, Stacy
• Application Number:
  US14/945,468
• Time in Patent Office: 509 Days
• Field of Search: 716116-117, 326 37- 38, 326 93, 326 96, 326 99, 327 39- 40, 327100, 327113, 327115-117
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/343 Logical level
• CPC Class Codes: H03K 19/01728 in synchronous circuits, i.e. by using clock signals
• CPC Class Codes: H03K 19/01855 synchronous, i.e. using clock signals
• CPC Class Codes: H03K 19/096 Synchronous circuits, i.e. using clock signals H03K19/01728, H03K19/01855 take precedence
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used
• CPC Class Codes: H03L 7/0991 the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814
• CPC Class Codes: H03L 7/16 Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H03L 7/197 a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division H03L7/1806 takes precedence

Abstract

Circuits of a TAF-DPS clock generator implemented on programmable logic chip comprise: 1) a base time unit generator created from configurable blocks, or on-chip PLL, or on-chip DLL, said base time unit generator produces a plurality of phase-evenly-spaced-signals; 2) a TAF-DPS frequency synthesizer created by configuring configurable blocks of said programmable logic chip, said TAF-DPS frequency synthesizer takes said plurality of phase-evenly-spaced-signals as its input. Methods of creating flexible clock signal to drive application comprise: 1) selecting one or more strategic areas in said programmable logic chip; 2) creating one or more TAF-DPS clock generator for each said area by using the configurable resource in said area; 3) creating control function to control the frequency and duty-cycle of the TAF-DPS clock generator output, said control function can be circuit created from configuring configurable blocks, said control function can also be achieved by software; 4) driving the circuits in application by the flexible clock generated from said TAF-DPS clock generator.

Claims

1. A TAF-DPS clock generator implemented on programmable logic chip, for generating a flexible clock signal, comprises:

a first input for receiving a frequency control word, said frequency control word is used to control frequency of said flexible clock signal;

a second input for receiving a duty-cycle control word, said duty-cycle control word is used to control duty-cycle of said flexible clock signal;

a third input for receiving a reference clock signal of a known frequency;

an output for delivering said flexible clock signal;

a base time unit generator, having an input for receiving said reference clock signal, having an output for delivering a plurality of K phase-evenly-spaced-signals with a predetermined frequency where K is an integer of greater than one, said base time unit generator is created using resource from said programmable logic chip, said base time unit is reconfigurable when instructed for changing the value of K and changing said predetermined frequency;

a TAF-DPS frequency synthesizer, having a frequency control word input for receiving said frequency control word from said first input, having a duty-cycle control word input for receiving said duty-cycle control word from said second input, having a third input for receiving said plurality of K phase-evenly-spaced-signals from said base time unit generator, having a clock output for delivering a synthesized flexible clock signal with desired frequency and desired duty-cycle, said TAF-DPS frequency synthesizer is created using resource from said programmable logic chip, said TAF-DPS frequency synthesizer is reconfigurable when instructed for accommodating a different K value;

wherein said clock output of said TAF-DPS frequency synthesizer is connected to said output.

2. The system of claim 1, wherein said base time unit generator is created from a divider chain, said divider chain comprises a series of flip-flips driven by said reference clock signal, said flip-flips are connected in series to form a loop, all non-inverting and inverting outputs from said flip-flips form said plurality of K phase-evenly-spaced-signals, said divider chain is created using configurable blocks of said programmable logic chip.

3. The system of claim 1, wherein said base time unit generator is created from a PLL, said PLL is resided in said programmable logic chip as a standard module, said PLL uses said reference clock signal as its input reference, said PLL is configured to operate at a predetermined frequency, said PLL has a VCO (voltage control oscillator) having multiple stages, all outputs from said stages form said plurality of K phase-evenly-spaced-signals.

4. The system of claim 1, wherein said base time unit generator is created from a DLL, said DLL is resided in said programmable logic chip as a standard module, said DLL uses said reference clock signal as its input, said DLL has a VCDL (voltage controlled delay line) having multiple stages, all outputs from said stages form said plurality of K phase-evenly-spaced-signals.

5. The system of claim 1, wherein said TAF-DPS frequency synthesizer comprises:

a first K→

1 multiplexer, having a multi-bit reference input for receiving said plurality of K phase-evenly-spaced-signals, having a control input, having an output;

a second K→

1 multiplexer, having a multi-bit reference input for receiving said plurality of K phase-evenly-spaced-signals, having a control input, having an output;

a 2→

1 multiplexer, having a first input for receiving the output from said first K→

1 multiplexer, having a second input for receiving the output from said second K→

1 multiplexer, having a control input, having an output;

a toggle flip-flop for generating a pulse train, comprises;

a D-type flip-flop, having a clock input for receiving output from the output of said 2→

1 multiplexer, having a data input, having an output for outputting a CLK1 signal;

an inverter, having an input for receiving said CLK1 signal, having an output for outputting a CLK2 signal;

wherein said CLK2 signal is connected to said data input of said D-type flip-flop;

wherein said CLK1 signal contains said pulse train;

a control logic block, having a first input for receiving said frequency control word, having a second input for receiving said duty-cycle control word, having a third input for receiving said CLK1 signal, having a fourth input for receiving said CLK2 signal, having a first output connected to said control input of said first K→

1 multiplexer, having a second output connected to said control input of said second K→

1 multiplexer;

wherein said CLK1 signal is connected to said control input of said 2→

1 multiplexer;

wherein said CLK1 signal is outputted as said synthesized flexible clock signal.

6. The system of claim 5, wherein said K→

1 multiplexers, said 2→

1 multiplexer, said control logic block and said toggle flip-flop are created by configuring configurable blocks from said programmable logic chip, wherein all interconnecting connections among circuits are created using resource of said programmable logic chip.

7. A method of creating TAF-DPS clock generators on a programmable logic chip, comprising the steps of:

selecting a plurality of areas in said programmable logic chip, said areas are distributed in strategic locations of said programmable logic chip, said strategic locations are chosen by user of said programmable logic chip;

creating at least one TAF-DPS clock generators for each said area;

driving functional circuits in each said areas by flexible clock signals generated from said TAF-DPS clock generators in each said area.

8. The method of claim 7, wherein the creating of TAF-DPS clock generator comprises the steps of:

creating a plurality of phase-evenly-spaced-signals from a base time unit;

creating a TAF-DPS frequency synthesizer by configuring configurable blocks of said programmable logic chip;

feeding said plurality of phase-evenly-spaced-signals to said TAF-DPS frequency synthesizer;

outputting flexible clock signal synthesized from said TAF-DPS frequency synthesizer as clock signal.

9. The method of claim 8, wherein the creating of said base time unit for generating a plurality of phase-evenly-spaced-signals comprises the steps of:

receiving a reference clock of known frequency;

creating a series of flip-flops by configuring configurable blocks in said programmable logic chip;

connecting said series of flip-flops as a loop;

driving said series of flip-flops by said reference clock of known frequency;

outputting all non-inverting and inverting outputs from said flip-flops as said plurality of phase-evenly-spaced-signals.

10. The method of claim 8, wherein the creating of base time unit comprises the steps of:

receiving a reference signal of known frequency;

selecting a PLL from said programmable logic chip;

locking said PLL to said reference signal of known frequency;

configuring said PLL to generate a plurality of outputs with a predetermined frequency;

outputting said plurality of outputs from said PLL as said plurality of phase-evenly-spaced-signals.

11. The method of claim 8, wherein the creating of base time unit comprises the steps of:

receiving a reference signal of known frequency;

selecting a DLL from said programmable logic chip;

locking said DLL to said reference signal of known frequency;

configuring said DLL to generate a plurality of outputs with a predetermined frequency;

outputting said plurality of outputs from said DLL as said plurality of phase-evenly-spaced-signals.

12. A method of driving circuits in an application by a flexible clock signal generated from a TAF-DPS clock generator, said TAF-DPS clock generator is implemented on a programmable logic chip, comprises the steps of:

creating a specification of requirement on clock signal performance for said application;

generating said flexible clock signal from said TAF-DPS clock generator, said TAF-DPS clock generator is created by using resource of said programmable logic chip;

programming frequency control word and duty-cycle control word of said TAF-DPS clock generator to generate said flexible clock signal, said flexible clock signal achieves the performance defined in said specification of requirement;

driving circuits in said application by said flexible clock signal.

13. The method of claim 12, wherein the programming of frequency control word and duty-cycle control word is accomplished by a control circuit, said control circuit is created by configuring configurable blocks resided on said programmable logic chip.

14. The method of claim 12, wherein the programming of frequency control word and duty-cycle control word is accomplished by software, said software is executed in a processor, said processor is incorporated in said application environment.