Data transmission method and system

• US 9,621,334 B2
• Filed: 09/17/2008
• Issued: 04/11/2017
• Est. Priority Date: 09/19/2007
• Status: Active Grant

• Current Assignee: HTC Corporation
• Original Assignee: HTC Corporation
• Inventors: Huang, David, Chang, Wei-Chih, Kuan, Tsung-Pao
• Primary Examiner(s): Washburn, Daniel
• Assistant Examiner(s): Hassan, Sarah
• Application Number:
  US12/212,418
• Publication Number:
  US 20090074122A1
• Time in Patent Office: 3,128 Days
• Field of Search: 375260, 375343, 370208
• CPC Class Codes: H04B 7/04 using two or more spaced independent antennas
• CPC Class Codes: H04L 7/02 Speed or phase control by the received code signals, the signals containing no special synchronisation information H04L7/0075 takes precedence
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A data transmission method for a data transmission system including a first device and a second device is disclosed. The method comprises the steps of transmitting a clock signal to synchronize the first device and the second device; transmitting a mode signal from the first device to the second device, wherein the mode signal indicates a transmission mode between the first device and the second device; and transmitting a serial data between the first device and the second device based on the clock signal, wherein the length of the serial data is determined based on the transmission mode.

Claims

1. A data transmission method for a data transmission system including a first device and a second device, comprising:

transmitting a clock signal to synchronize the first device and the second device wherein the second device includes a buffer and a memory;

transmitting a mode signal from the first device to the second device, wherein the mode signal indicates a transmission mode between the first device and the second device; and

transmitting a serial data between the first device and the second device based on the clock signal,

wherein the serial data comprises a plurality of bits for representing a plurality of serial data, at least part of the plurality of bits constituting a control signal, and the control signal has different numbers of bits in each serial data corresponding to different transmission modes,

wherein a length of the control signal is determined based on the mode signal, and the length of the control signal is not zero, and

wherein when the transmission mode is a first transmission mode, the control signal comprises m bits where m is equal to finite number for indicating a memory address.

2. The method as claimed in claim 1, wherein when the transmission mode is a second transmission mode, the control signal comprises n bits for indicating whether a buffer is full and m is larger than n where m and n are equal to a finite number.

3. The method as claimed in claim 1, further comprising:

transmitting an acknowledge signal from the second device to the first device to inform the first device that the second device has received the control signal.

4. A data transmission system, comprising:

a first device;

a second device including a buffer and a memory;

a clock signal line, coupled between the first device and the second device, for transmitting a clock signal to synchronize the first device and the second device; and

a data line for transmitting a mode signal from the first device to the second device and for transmitting a serial data between the first device and the second device based on the clock signal;

wherein the mode signal indicates a transmission mode between the first device and the second device, and the serial data comprises a plurality of bits for representing a plurality of serial data, at least part of the plurality of bits constituting a control signal, and the control signal has different numbers of bits in each serial data corresponding to different transmission modes,

wherein a length of the control signal is determined based on the mode signal, and the length of the control signal is not zero, and

wherein when the transmission mode is a first transmission mode, the control signal comprises m bits for indicating a memory address.

5. The system as claimed in claim 4, wherein the data line is further configured to transmit at least one bit between the first device and the second device for indicating a writing or reading operation in the buffer.

6. The system as claimed in claim 4, wherein the data line is further configured to transmit at least one bit from the second device to the first device for indicating an acknowledge signal to inform the first device that the second device has received the control signal.

7. A data transmission system, comprising:

a first device;

a second device including a buffer and a memory;

a clock signal line, coupled between the first device and the second device, for transmitting a clock signal to synchronize the first device and the second device; and

a data line for transmitting a mode signal from the first device to the second device and for transmitting a plurality of serial data between the first device and the second device based on the clock signal,

wherein the mode signal indicates a transmission mode between the first device and the second device, and the length of each serial data is determined based on the transmission mode,

wherein the data line is further configured to transmit a control signal from the first device to the second device based on the clock signal,

wherein the length of the control signal is determined based on the mode signal, and,

wherein when the transmission mode is a second transmission mode, the control signal comprises n bits where n is equal to a finite number for indicating whether the buffer is full.