System and method for sub-column parallel digitizers for hybrid stacked image sensor using vertical interconnects

• US 9,622,650 B2
• Filed: 05/14/2012
• Issued: 04/18/2017
• Est. Priority Date: 05/12/2011
• Status: Active Grant

• Current Assignee: Depuy Synthes Products Incorporated (Johnson & Johnson)
• Original Assignee: Depuy Synthes Products Incorporated (Johnson & Johnson)
• Inventors: Blanquart, Laurent
• Primary Examiner(s): Bui-Pho, Pascal M
• Application Number:
  US13/471,432
• Publication Number:
  US 20130126709A1
• Time in Patent Office: 1,800 Days
• Field of Search: 2502081, 2502141, 250214 R, 250239, 348272-283, 348294-324, 257414, 257431-466
• CPC Class Codes: A61B 1/00009 of image signals during a use of endoscope
• CPC Class Codes: A61B 1/051 Details of CCD assembly
• CPC Class Codes: A61B 1/0676 at distal tip of an endoscope
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/28 Structure, shape, material or disposition of the layer connectors prior to the connecting process
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/146 Imager structures
• CPC Class Codes: H01L 27/14601 Structural or functional details thereof
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14638 Structures specially adapted for transferring the charges across the imager perpendicular to the imaging plane
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14641 Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 27/1469 : Assemblies, i.e. hybrid integration
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/381 : Pitch distance
• CPC Class Codes: H01L 31/028 : including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 31/0296 : including, apart from doping material or other impurities, only AIIBVI compounds, e.g. CdS, ZnS, HgCdTe
• CPC Class Codes: H01L 31/0304 : including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H04N 23/555 : for picking-up images in sites, inaccessible due to their dimensions or hazardous conditions, e.g. endoscopes or borescopes
• CPC Class Codes: H04N 23/56 : provided with illuminating means
• CPC Class Codes: H04N 25/75 : Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/767 : Horizontal readout lines, multiplexers or registers
• CPC Class Codes: H04N 25/772 : comprising A/D, V/T, V/F, I/T or I/F converters
• CPC Class Codes: H04N 25/778 : comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
• CPC Class Codes: H04N 25/79 : Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors

Abstract

Embodiments of a hybrid imaging sensor and methods for pixel sub-column data read from the within a pixel array.

Claims

1. An imaging sensor comprising:

a plurality of substrates;

a pixel array comprising pixels formed into a plurality of pixel columns, wherein each of said plurality of pixel columns is divided into a plurality of pixel sub-columns that are independent and distinct, wherein each pixel sub-column comprises a plurality of pixels, wherein each pixel sub-column has a pixel sub-column bus;

a plurality of supporting circuits formed into a plurality of supporting circuit columns, wherein each of said plurality of supporting circuit columns is divided into a plurality of circuit sub-columns that are independent and distinct, wherein each circuit sub-column has a circuit bus, wherein one pixel sub-column bus corresponds with one circuit bus;

wherein a first substrate of the plurality of substrates comprises the pixel array;

wherein the plurality of supporting circuits is disposed on a second substrate that is disposed remotely relative to said first substrate;

wherein each of said plurality of circuit sub-columns is electrically connected to, and in electrical communication with, a corresponding pixel sub-column of said pixel array; and

wherein said electrical communication is provided by an interconnect for each pixel sub-column bus and corresponding circuit bus disposed between said first substrate and said second substrate, such that each of the pixel sub-columns is read independently.

2. The imaging sensor of claim 1, wherein each pixel sub-column bus and each circuit bus are superimposed, such that each pixel sub-column bus and each circuit bus are substantially aligned;

and

wherein the interconnect is located anywhere along the superimposed pixel sub-column bus and circuit bus.

3. The imaging sensor of claim 2, wherein the electrical connection between one pixel sub-column bus and one circuit bus is accomplished by a plurality of interconnects.

4. The imaging sensor of claim 1, wherein said imaging sensor is backside illuminated.

5. The imaging sensor of claim 1, wherein the plurality of substrates further comprise a plurality of subsequent supporting substrates.

6. The imaging sensor of claim 1, wherein each pixel sub-column is electronically isolated from other pixel sub-columns.

7. The imaging sensor of claim 1, wherein said second substrate comprises support circuits dedicated and corresponding to each pixel sub-column of the pixel array.

8. The imaging sensor of claim 1, wherein said pixel sub-columns are electrically configured to be read at substantially the same time.

9. A method of accessing data on an imaging sensor comprising:

electronically connecting pixels in a pixel array located on a first substrate to support circuits on a second substrate;

wherein said pixel array is organized into pixel columns;

wherein each of said pixel columns is divided into a plurality of pixel sub-columns that are independent and distinct, wherein each pixel sub-column comprises a plurality of pixels, wherein each pixel sub-column has a pixel sub-column bus;

reading the plurality of pixel sub-columns starting with a first pixel in each sub-column and sequentially reading pixel data from each of the pixels until the last pixel in the sub-column is read;

transmitting said pixel data for each pixel sub-column through an interconnect to a corresponding circuit sub-column located on the second substrate, wherein the second substrate comprises a plurality of circuit columns, wherein each of said plurality of circuit columns is divided into a plurality of circuit sub-columns that are independent and distinct, wherein each circuit sub-column has a circuit bus, wherein one pixel sub-column bus corresponds with one circuit bus;

wherein the data from each pixel sub-column is processed by the circuit sub-column corresponding with each of said pixel sub-column,

processing said pixel data into an image.

10. The method of accessing data on an imaging sensor of claim 9, further comprising reading pixel data from each pixel sub-column simultaneously.

11. The method of accessing data on an imaging sensor of claim 9, further comprising transmitting said pixel data to a support circuit that corresponds to a plurality of pixel sub-columns from within the same pixel column.

26. The method of accessing data on an imaging sensor of claim 9, further comprising transmitting said pixel data from one of the plurality of pixel sub-columns to a support circuit having a support circuit area and size that is the same as the pixel sub-column area and size.

12. An imaging sensor comprising:

a plurality of substrates comprising at least a first substrate and a second substrate;

a pixel array located on the first substrate and comprising a plurality of pixel columns, wherein each of the plurality of pixel columns is defined as a plurality of pixels in length enough to cover the dimension of the array;

wherein each of said pixel columns is divided into a plurality of pixel sub-columns, wherein each pixel sub-column comprises a plurality of pixels, such that each pixel sub-column is electrically isolated from other pixel sub-columns;

a plurality of supporting circuits located on the second substrate and comprising a plurality of circuit columns, wherein the plurality of circuit columns is divided into a plurality of circuit sub-columns that are independent and distinct where one circuit sub-column corresponds with one pixel sub-column, wherein each of the plurality of circuit sub-columns is defined as having an area and size that corresponds with an area and size of a corresponding pixel sub-column;

a plurality of buses, wherein there is one pixel sub-column bus per at least one pixel sub-column residing on the first substrate and one circuit column bus per at least one circuit sub-column residing on said second substrate;

wherein at least a portion of each of the pixel sub-column buses is superimposed with at least a portion of each of the corresponding circuit column buses and at least one interconnect providing electrical communication between one pixel sub-column bus and one corresponding circuit column bus; and

wherein said at least one interconnect is located anywhere along the superimposition of the pixel sub-column bus and the corresponding circuit column bus.

13. The imaging sensor of claim 12, further comprising a plurality interconnects disposed between said substrates and wherein said plurality of interconnects are spaced relative to one another at a distance that is greater than a pixel pitch of said pixel array.

14. The imaging sensor of claim 12, wherein the first substrate and second substrate are in alignment.

15. The imaging sensor of claim 12, wherein an area of one of said pixel sub-columns on said first substrate is substantially equal to an area of one of said corresponding circuit sub-columns on said second substrate.

16. The imaging sensor of claim 12, wherein said second substrate is substantially the same size as said first substrate.

17. The imaging sensor of claim 12, wherein an area of one of said pixel sub-columns on said first substrate is larger than an area of one of said corresponding circuit sub-columns on said second substrate.

18. The imaging sensor of claim 12, wherein an area of one of said pixel sub-columns on said first substrate is smaller than an area of one of said corresponding circuit sub-columns on said second substrate.

19. The imaging sensor of claim 12, wherein an aspect ratio of one of said pixel sub-columns is substantially similar to an aspect ratio of one of said circuit sub-columns.

20. The imaging sensor of claim 12, wherein a plurality of interconnects connect a pixel sub-column bus to a corresponding circuit column bus.

21. The imaging sensor of claim 12, wherein an aspect ratio of one of said pixel sub-columns is different than an aspect ratio of one of said circuit sub-columns.

22. The imaging sensor of claim 12, wherein the aspect ratio of at least one of said circuit sub-columns is “

N”

pixels wide and 1/“

M”

pixels in length of the aspect ratio of one of said pixel sub-columns.

23. The imaging sensor of claim 12, wherein the aspect ratio of at least one of said circuit sub-columns is two times wider than and one-half the length of the aspect ratio of one of said pixel sub-columns.

24. The imaging sensor of claim 12, wherein the aspect ratio of at least one of said circuit sub-columns is four times wider than and one-fourth the length of the aspect ratio of one of said pixel sub-columns.

25. The imaging sensor of claim 12, wherein the aspect ratio of at least one of said circuit sub-columns is eight times wider than and one-eighth the length of the aspect ratio of one of said pixel sub-columns.

27. An imaging sensor comprising:

a plurality of substrates comprising a first substrate and a second, supporting substrate;

a pixel array comprising pixels formed into pixel columns, wherein each of the pixel columns is divided into a plurality of pixel sub-columns that are independent and distinct, wherein each pixel sub-column comprises a plurality of pixels, wherein each pixel sub-column has a corresponding pixel sub-column bus;

a plurality of supporting circuits formed into a plurality of supporting circuit columns, wherein each of the supporting circuit columns is divided into a plurality of circuit sub-columns that are independent and distinct, wherein each circuit sub-column has a corresponding circuit bus, wherein one pixel sub-column bus corresponds with one circuit bus;

wherein the first substrate comprises the pixel array and the pixel sub-column buses;

wherein the second, supporting substrate is disposed remotely relative to the first substrate and comprises the plurality of supporting circuits and the circuit buses;

wherein each of the circuit sub-columns is electrically connected to, and in electrical communication with, a corresponding pixel sub-column of the pixel array; and

wherein the electrical communication is provided by a single interconnect for each pixel sub-column bus and corresponding circuit bus disposed between the first substrate and the second, supporting substrate such that each of the pixel sub-columns is read independently.