Efficient error handling mechanisms in data storage systems

• US 9,626,118 B2
• Filed: 12/07/2015
• Issued: 04/18/2017
• Est. Priority Date: 06/26/2012
• Status: Active Grant

• Current Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Lam, Johnny A.
• Primary Examiner(s): Tabone, Jr., John J
• Application Number:
  US14/961,856
• Publication Number:
  US 20160085470A1
• Time in Patent Office: 498 Days
• Field of Search: 714799, 714773, 714763, 714768, 714702, 714718, 714723, 714742, 714 624, 714 48, 711202, 711206, 711103, 707813, 707824, 702 59, 702117, 702118
• CPC Class Codes: G06F 11/0703 Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 11/1016 Error in accessing a memory location, i.e. addressing error
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0873 Mapping of cache memory to specific storage devices or parts thereof
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1054 the data cache being concurrently physically addressed
• CPC Class Codes: G06F 13/404 with address mapping
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0644 : Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0655 : Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0685 : Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 3/0688 : Non-volatile semiconductor memory arrays
• CPC Class Codes: G06F 8/441 : Register allocation; Assignment of physical memory space to logical memory space
• CPC Class Codes: G11C 11/5628 : Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 2029/4402 : Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/00 : Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/52 : Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/76 : using address translation or modifications
• CPC Class Codes: G11C 8/06 : Address interface arrangements, e.g. address buffers

Abstract

A data storage system configured to efficiently search and update system data is disclosed. In one embodiment, the data storage system can attempt to correct errors in retrieved data configured to index system data. Metadata stored along with user data in a memory location can be configured to indicate a logical address associated in a logical-to-physical location mapping with a physical address at which user data and metadata are stored. The data storage system can generate modified versions of logical address indicated by the metadata and determine whether such modified versions match the physical address in the logical-to-physical mapping. Modified versions of the logical address can be generated by flipping one or more bits in the logical address indicated by the metadata. Efficiency can do increased and improved performance can be attained.

Claims

1. A non-volatile data storage system, comprising:

a non-volatile memory array comprising a plurality of physical locations configured to store user data and metadata; and

a controller configured to;

maintain a mapping associating a set of physical addresses corresponding to the plurality of physical locations in the non-volatile memory array with a set of logical addresses, the mapping indexed by the set of logical addresses;

process first user data stored at a first physical location of the plurality of physical locations;

determine in the mapping that a first logical address of the set of logical addresses read from metadata stored at the first physical location is not associated with a first physical address of the set of physical addresses corresponding to the first physical location;

generate a second logical address of the set of logical addresses by performing one or more error corrections of a plurality of error corrections on the first logical address read from the metadata stored at the first physical location, the second logical address determined in the mapping to be associated with the first physical address; and

update the mapping at the second logical address based on the processed first user data.

2. The non-volatile data storage system of claim 1, wherein the controller is configured to perform the one or more error corrections of the plurality of error corrections on the first logical address in a predetermined order.

3. The non-volatile data storage system of claim 2, wherein the predetermined order is based on an error likelihood.

4. The non-volatile data storage system of claim 2, wherein the plurality of error corrections comprise a first set of error corrections flipping m-bits of the first logical address, where m is a natural number.

5. The non-volatile data storage system of claim 4, wherein the plurality of error corrections further comprise a second set of error corrections flipping m+1 bits of the first logical address.

6. The non-volatile data storage system of claim 1, wherein the controller is configured to process the first user data by moving the first user data to a second physical location of the plurality of physical locations, and

wherein the controller is configured to update the mapping to associate the second logical address with a second physical address corresponding to the second physical location.

7. The non-volatile data storage system of claim 1, wherein the controller is configured to process the first user data by determining the first user data is unrecoverable from the first physical location, and

wherein the controller is configured to update the mapping to disassociate the second logical address from the first physical address.

21. The controller of claim 1, wherein the controller is further configured to process the first user data by determining the first user data is unrecoverable from the first physical location, and

wherein the controller is further configured to update the mapping to disassociate the second logical address from the first physical address.

8. A method comprising:

maintaining a mapping associating a set of physical addresses corresponding to a plurality of physical locations in a non-volatile memory array with a set of logical addresses, the mapping indexed by the set of logical addresses;

processing first user data stored at a first physical location of the plurality of physical locations;

determining in the mapping that a first logical address of the set of logical addresses read from metadata stored at the first physical location is not associated with a first physical address of the set of physical addresses corresponding to the first physical location;

generating a second logical address of the set of logical addresses by performing one or more error corrections of a plurality of error corrections on the first logical address read from the metadata stored at the first physical location, the second logical address determined in the mapping to be associated with the first physical address; and

updating the mapping at the second logical address based on the processed first user data.

9. The method of claim 8, wherein the one or more error corrections of the plurality of error corrections on the first logical address are performed in a predetermined order.

10. The method of claim 9, wherein the predetermined order is based on an error likelihood.

11. The method of claim 9, wherein the plurality of error corrections comprise a first set of error corrections flipping m-bits of the first logical address, where m is a natural number.

12. The method of claim 11, wherein the plurality of error corrections further comprise a second set of error corrections flipping m+1 bits of the first logical address.

13. The method of claim 8, wherein processing the first user data comprises moving the first user data to a second physical location of the plurality of physical locations, and

wherein updating the mapping comprises updating the mapping to associate the second logical address with a second physical address corresponding to the second physical location.

14. The method of claim 8, wherein processing the first user data comprises determining the first user data is unrecoverable from the first physical location, and

wherein updating the mapping comprises updating the mapping to disassociate the second logical address from the first physical address.

15. A controller for a non-volatile storage system, the controller configured to:

maintain a mapping associating a set of physical addresses corresponding to a plurality of physical locations in a non-volatile memory array with a set of logical addresses, the mapping indexed by the set of logical addresses;

process first user data stored at a first physical location of the plurality of physical locations;

determine in the mapping that a first logical address of the set of logical addresses read from metadata stored at the first physical location is not associated with a first physical address of the set of physical addresses corresponding to the first physical location;

generate a second logical address of the set of logical addresses by performing one or more error corrections of a plurality of error corrections on the first logical address read from the metadata stored at the first physical location, the second logical address determined in the mapping to be associated with the first physical address; and

update the mapping at the second logical address based on the processed first user data.

16. The controller of claim 15, wherein the controller is further configured to perform the one or more error corrections of the plurality of error corrections on the first logical address in a predetermined order.

17. The controller of claim 16, wherein the predetermined order is based on an error likelihood.

18. The controller of claim 16, wherein the plurality of error corrections comprise a first set of error corrections flipping m-bits of the first logical address, where m is a natural number.

19. The controller of claim 18, wherein the plurality of error corrections further comprise a second set of error corrections flipping m+1 bits of the first logical address.

20. The controller of claim 15, wherein the controller is further configured to process the first user data by moving the first user data to a second physical location of the plurality of physical locations, and

wherein the controller is further configured to update the mapping to associate the second logical address with a second physical address corresponding to the second physical location.