Apparatus for reducing write minimum supply voltage for memory

• US 9,627,039 B2
• Filed: 08/19/2015
• Issued: 04/18/2017
• Est. Priority Date: 06/28/2012
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Kulkarni, Jaydeep P, Geuskens, Bibiche M, Khellah, Muhammad M, Tschanz, James W, De, Vivek K
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Bashar, Mohammed A
• Application Number:
  US14/830,679
• Publication Number:
  US 20160141022A1
• Time in Patent Office: 608 Days
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/227 Timing of memory operations based on dummy memory elements or replica circuits

Abstract

Described is an apparatus for self-induced reduction in write minimum supply voltage for a memory element. The apparatus comprises: a memory element having cross-coupled inverters coupled to a first supply node; a power device coupled to the first supply node and a second supply node, the second supply node coupled to power supply; and an access device having a gate terminal coupled to a word-line, a first terminal coupled to the memory element, and a second terminal coupled to a bit-line which is operable to be pre-discharged to a logical low level prior to write operation.

Claims

1. An apparatus comprising:

a power transistor coupled to a power supply node;

first and second write bit-lines which are to be pre-discharged to a logical low level before write operation, the first and second write bit-lines coupled to a memory cell which is coupled to the power supply node; and

first circuitry to generate a control signal to turn off the power transistor when the first and second write bit-lines are pre-discharged to the logical low level and during write operation.

2. The apparatus of claim 1, wherein the first circuitry comprises:

a logical NOR gate which is to apply a logical NOR operation on the first and second write bit-lines.

3. The apparatus of claim 2, wherein the first circuitry comprises:

a logical AND gate which is to receive an output of the logical NOR gate and to perform an AND operation with the output and a write word-line.

4. The apparatus of claim 1, wherein the first circuitry comprises a pulse generating logic, and wherein the control signal is a pulse signal.

5. The apparatus of claim 1, comprises a second circuitry which is to delay at least one of the first or second write bit-lines relative to a write word-line.

6. The apparatus of claim 5, wherein the second circuitry has a programmable delay.

7. The apparatus of claim 5, wherein the second circuitry is to delay the at least one of the first or second write bit-lines relative to the write word-line by a fraction of a clock phase.

8. The apparatus of claim 7, wherein the fraction of the clock phase is in a range of 20% to 30% of the clock phase.

9. The apparatus of claim 1, wherein the memory cell is one of a 6T SRAM cell or 8T SRAM cell.

10. The apparatus of claim 1, wherein the power transistor is also coupled to another power supply node.

11. The apparatus of claim 1, wherein the first and second write bit-lines are to be pre-discharged to a logic low level during an inactive state of a column of memory cells.

12. A system comprising:

a processor;

a memory coupled to the processor, the memory including;

a power transistor coupled to a power supply node;

first and second write bit-lines which are to be pre-discharged to a logical low level before write operation, the first and second write bit-lines coupled to a memory cell which is coupled to the power supply node; and

first circuitry to generate a control signal to turn off the power transistor when the first and second write bit-lines are pre-discharged to the logical low level and during write operation; and

a wireless interface for allowing the processor to communicate with another device.

13. The system of claim 12, wherein the first circuitry comprises:

a logical NOR gate which is to apply a logical NOR operation on the first and second write bit-lines; and

a logical AND gate which is to receive an output of the logical NOR gate and to perform an AND operation with the output and a write word-line.

14. The system of claim 12, wherein the first circuitry comprises a pulse generating logic, and wherein the control signal is a pulse signal.

15. The system of claim 12 comprises a second circuitry which is to delay at least one of the first or second write bit-lines relative to a write word-line.

16. The system of claim 15, wherein the second circuitry is to delay the at least one of the first or second write bit-lines relative to the write word-line by a fraction of a clock phase.

17. The apparatus of claim 16, wherein the fraction of the clock phase is in a range of 20% to 30% of the clock phase.

18. The system of claim 12, wherein the memory is one of a 6T SRAM or 8T SRAM.

19. An apparatus comprising:

a memory cell having bit-cell nodes coupled to pull-up devices and access transistors; and

first and second write bit-lines which are to be pre-discharged to a logical low level before write operation, wherein the first and second write bit-lines are coupled to the memory cell, wherein the bit-cell nodes are to be discharged to logical low level when the access transistors are to be turned on.

20. The apparatus of claim 19, wherein the pull-up devices cause power supply droop on a power supply node coupled to the memory cell.