Systems, methods, and apparatus for memory cells with common source lines

• US 9,627,073 B2
• Filed: 09/20/2016
• Issued: 04/18/2017
• Est. Priority Date: 12/02/2013
• Status: Active Grant

• Current Assignee: Longitude Flash Memory Solutions, Ltd. (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Yu, Xiaojun, Prabhakar, Venkatraman, Kouznetsov, Igor G., Hinh, Long, Jin, Bo
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US15/271,028
• Publication Number:
  US 20170011800A1
• Time in Patent Office: 210 Days
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause a change in a charge storage layer included in the first transistor.

Claims

1. A system comprising:

a processor;

at least one voltage source; and

a memory array;

wherein;

the processor is configured to provide control signals to the at least one voltage source and the memory array;

the at least one voltage source is configured to generate a plurality of voltages, wherein the plurality of voltages comprises at least one voltage of at least 3.5V; and

the memory array comprises;

a first memory cell comprising a first transistor coupled to a second transistor, wherein the first transistor comprises a memory element; and

a second memory cell comprising a third transistor coupled to a fourth transistor;

wherein, in response to an initiation of a programming operation, the memory array receives at least one of the plurality voltages at each of a drain of the first transistor, a drain of the third transistor, a gate of the second transistor, a gate of the fourth transistor, and a gate of the first transistor, and

wherein receiving the voltages results in a change in one or more electrical characteristics of the memory element.

2. The system of claim 1, wherein the plurality of voltages further comprises at least one voltage of 1V.

3. The system of claim 1, wherein the memory array is part of a flash memory.

4. The system of claim 1, further comprising a control circuitry comprising the at least one voltage source.

5. The system of claim 4, wherein the control circuitry is configured to provide the plurality of voltages to the memory array.