Semiconductor memory device
First Claim
1. A semiconductor memory device, comprising:
- a memory block including a plurality of memory strings, the plurality of memory strings including a first memory string and a second memory string;
a first bit line connected to one terminal of the first memory string and one terminal of the second memory string;
a plurality of word lines connected to the plurality of memory strings; and
a controller configured to control an erase operation of the memory block, wherein the erase operation includes;
applying a first erase voltage to the plurality of word lines;
selecting the first memory string at a first time;
while the first memory string is selected, applying an erase verify voltage to the plurality of word lines and reading data of the first memory string; and
selecting the second memory string at a second time without making the voltage applied to the plurality of word lines zero voltage for any time between the first time and the second time.
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Accused Products
Abstract
A semiconductor memory device has a memory block including memory strings with first and second selection transistors at opposite ends of the memory strings. A bit line is connected to the first selection transistor of each memory string and a sense amplifier is connected to the bit line. The memory block includes word lines connected to each memory cell transistor in the memory strings. The memory device also includes a controller to control an erase operation that includes applying an erase voltage to the word lines, addressing a first memory string by applying a selection voltage to a gate electrode of first and second selection transistors of the first memory string, then applying an erase verify voltage to the word lines and using the sense amplifier to read data of memory cell transistors in the first memory string, then addressing a second memory string without first discharging the word lines.
27 Citations
20 Claims
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1. A semiconductor memory device, comprising:
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a memory block including a plurality of memory strings, the plurality of memory strings including a first memory string and a second memory string; a first bit line connected to one terminal of the first memory string and one terminal of the second memory string; a plurality of word lines connected to the plurality of memory strings; and a controller configured to control an erase operation of the memory block, wherein the erase operation includes; applying a first erase voltage to the plurality of word lines; selecting the first memory string at a first time; while the first memory string is selected, applying an erase verify voltage to the plurality of word lines and reading data of the first memory string; and selecting the second memory string at a second time without making the voltage applied to the plurality of word lines zero voltage for any time between the first time and the second time. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A semiconductor memory device, comprising:
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a memory block including a plurality of memory strings, the plurality of memory strings including a first memory string and a second memory string; a first bit line connected to one terminal of the first memory string and one terminal of the second memory string; a plurality of word lines connected to the plurality of memory strings; and a controller configured to control an erase operation of the memory block, wherein the erase operation includes; applying a first erase voltage to the plurality of word lines; selecting the first memory string; applying an erase verify voltage to the plurality of word lines; and selecting the second memory string, wherein the erase operation includes a first time period during which the controller does not make the voltage applied to the plurality of word lines zero voltage, and the steps of selecting the first memory string and selecting the second memory string are executed during the first time period. - View Dependent Claims (13, 14, 15, 16, 17)
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18. A semiconductor memory device, comprising:
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a memory block including a plurality of memory strings, the plurality of memory strings including a first memory string and a second memory string; a first bit line connected to one terminal of the first memory string and one terminal of the second memory string; a plurality of word lines connected to the plurality of memory strings; and a controller configured to control an erase operation of the memory block, wherein the erase operation includes first and second operations executed in sequence, wherein the first operation includes applying an erase voltage to the plurality of word lines, and the second operation includes; selecting the first memory string at a first time; while the first memory string is selected, applying an erase verify voltage to the plurality of word lines and reading data of the first memory string; and selecting the second memory string at a second time without zeroing out the voltage applied to the plurality of word lines during any time between the first time and the second time. - View Dependent Claims (19, 20)
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Specification