Shift register, gate driving circuit, and display device

• US 9,627,089 B2
• Filed: 07/31/2014
• Issued: 04/18/2017
• Est. Priority Date: 04/18/2014
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd., Chengdu BOE Optoelectronics Technology Company Limited (BOE Technology Group Co., Ltd.)
• Original Assignee: BOE Technology Group Co., Ltd., Chengdu BOE Optoelectronics Technology Company Limited (BOE Technology Group Co., Ltd.)
• Inventors: Qi, Xiaojing, Wu, Bo
• Primary Examiner(s): Lam, Tuan T
• Application Number:
  US14/448,076
• Publication Number:
  US 20150302934A1
• Time in Patent Office: 992 Days
• Field of Search: None
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G11C 19/184 with field-effect transistors, e.g. MOS-FET
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

The present invention provides a shift register, a gate driving circuit and a display device. The shift register comprises a precharge and reset module, a pull-up module, a pull-down module and a cut-off module, the cut-off module, the pull-up module and the pull-down module are connected at a first node, and the cut-off module is connected between the first node and the precharge and reset module. In the present invention, the cut-off module is provided to disconnect electric connection between the precharge and reset module and the pull-up module, such that the first node cannot discharge through the precharge and reset module, which effectively avoids internal discharge of the shift register, and further ensures normal output of the signal output from the output terminal of the shift register, and improves stability of the shift register.

Claims

1. A shift register, comprising:

a precharge and reset module, configured to precharge or reset a pull-up module according to a start signal input via a start signal input terminal or a reset signal input via a reset signal input terminal;

the pull-up module, configured to pull up a signal output by an output terminal of the shift register;

a first capacitor, configured to boost a voltage of a control terminal of the pull-up module in a pull-up stage;

a pull-down module, configured to pull down a signal output by the output terminal of the shift register; and

a cut-off module, configured to disconnect electric connection between the precharge and reset module and the pull-up module in the pull-up stage,

wherein the precharge and reset module is connected to a first power source and a second power source, the pull-up module is connected to a first clock signal terminal, a first terminal of the first capacitor is connected to the control terminal of the pull-up module, a second terminal of the first capacitor is connected to the output terminal of the shift register, the pull-down module is connected to a third power source, the cut-off module, the pull-up module and the pull-down module are connected at a first node, the pull-up module and the pull-down module are connected to the output terminal of the shift register, the cut-off module is connected between the first node and the precharge and reset module, and the pull-up module and cut-off module are also connected at a second node; and

wherein the cut-off module comprises;

a ninth TFT, a tenth TFT, a third capacitor and a fourth power source,

a gate of the ninth TFT is connected to the fourth power source, a source of the ninth TFT is connected to the precharge and reset module, a drain of the ninth TFT and a source of the tenth TFT are connected at the second node;

a gate of the tenth TFT is connected to the fourth power source, the source of the tenth TFT is connected to a first terminal of the third capacitor, and a drain of the tenth TFT is connected to the first node; and

a second terminal of the third capacitor is connected to the output terminal of the shift register.

2. The shift register according to claim 1, wherein the second power source supplies a second power signal whose voltage is VGL, the third power source supplies a third power signal whose voltage is VGL1, and VGL1≦

VGL.

3. The shift register according to claim 1, wherein, the first power source supplies a first power signal whose voltage is VGH, the fourth power source supplies a fourth power signal whose voltage is VGH1, and VGH1≧

VGH.

4. The shift register according to claim 3, wherein, the cut-off module further comprises:

a fourth capacitor,

a first terminal of the fourth capacitor is connected to the first terminal of the third capacitor and a second terminal of the fourth capacitor is connected to the third power source.

5. The shift register according to claim 1, wherein, a first clock signal is input via the first clock signal terminal, a high-level voltage of the first clock signal is equal to the voltage of the fourth power signal supplied from the fourth power source, and a low-level voltage of the first clock signal is equal to the voltage of the third power signal supplied form the third power source.

6. The shift register according to claim 5, wherein, the cut-off module further comprises:

a fourth capacitor,

a first terminal of the fourth capacitor is connected to the first terminal of the third capacitor and a second terminal of the fourth capacitor is connected to the third power source.

7. The shift register according to claim 6, wherein, the precharge and reset module comprises:

a first TFT and a second TFT,

a gate of the first TFT is connected to the start signal input terminal, a source of the first TFT is connected to the first power source, and the drain of the first TFT is connected to the cut-off module; and

a gate of the second TFT is connected to the reset signal input terminal, a source of the second TFT is connected to the second power source, and the drain of the second TFT is connected to the cut-off module.

8. The shift register according to claim 7, wherein, the pull-up module comprises:

a third TFT and an eighth TFT,

a gate of the third TFT is connected to the first node, a source of the third TFT is connected to the first clock signal terminal, and a drain of the third TFT is connected to the output terminal of the shift register; and

a gate of the eighth TFT is connected to the cut-off module, a source of the eighth TFT is connected to the first clock signal terminal, and a drain of the eighth TFT is connected to the output terminal of the shift register.

9. The shift register according to claim 8, wherein, the pull-down module comprises:

a fourth TFT, a fifth TFT, a sixth TFT, a seventh TFT, a second capacitor and a fifth power source,

a gate of the fourth TFT is connected to a second clock signal terminal, a source of the fourth TFT is connected to the third power source, and a drain of the fourth TFT is connected to the output terminal of the shift register;

a gate of the fifth TFT is connected to the first node, a source of the fifth TFT is connected to the fifth power source, and a drain of the fifth TFT is connected to a second terminal of the second capacitor;

a gate of the sixth TFT is connected to the drain of the fifth TFT, a source of the sixth TFT is connected to the third power source, and a drain of the sixth TFT is connected to the output terminal of the shift register;

a gate of the seventh TFT is connected to the drain of the fifth TFT, a source of the seventh TFT is connected to the third power source, and a drain of the seventh TFT is connected to the first node;

a first terminal of the second capacitor is connected to the first clock signal terminal; and

a second clock signal input via the second clock signal terminal is opposite to a first clock signal input via the first clock signal terminal in phase.

10. The shift register according to claim 9, wherein, the second power source supplies a second power signal whose voltage is VGL, the third power source supplies the third power signal whose voltage is VGL1, the fifth power source supplies a fifth power signal whose voltage is VGL2, and VGL2≦

VGL1≦

VGL.

11. The shift register according to claim 1, wherein, the cut-off module further comprises:

a fourth capacitor,

a first terminal of the fourth capacitor is connected to the first terminal of the third capacitor and a second terminal of the fourth capacitor is connected to the third power source.

12. The shift register according to claim 1, wherein, the precharge and reset module comprises:

a first TFT and a second TFT,

a gate of the first TFT is connected to the start signal input terminal, a source of the first TFT is connected to the first power source, and a drain of the first TFT is connected to the cut-off module; and

a gate of the second TFT is connected to the reset signal input terminal, a source of the second TFT is connected to the second power source, and a drain of the second TFT is connected to the cut-off module.

13. The shift register according to claim 1, wherein, the pull-up module comprises:

a third TFT and an eighth TFT,

a gate of the third TFT is connected to the first node, a source of the third TFT is connected to the first clock signal terminal, and a drain of the third TFT is connected to the output terminal of the shift register; and

a gate of the eighth TFT is connected to the second node, a source of the eighth TFT is connected to the first clock signal terminal, and a drain of the eighth TFT is connected to the output terminal of the shift register.

14. The shift register according to claim 1, wherein, the pull-down module comprises:

a fourth TFT, a fifth TFT, a sixth TFT, a seventh TFT, a second capacitor and a fifth power source,

a gate of the fourth TFT is connected to a second clock signal terminal, a source of the fourth TFT is connected to the third power source, and a drain of the fourth TFT is connected to the output terminal of the shift register;

a gate of the fifth TFT is connected to the first node, a source of the fifth TFT is connected to the fifth power source, and a drain of the fifth TFT is connected to a second terminal of the second capacitor;

a gate of the sixth TFT is connected to the drain of the fifth TFT, a source of the sixth TFT is connected to the third power source, and a drain of the sixth TFT is connected to the output terminal of the shift register;

a gate of the seventh TFT is connected to the drain of the fifth TFT, a source of the seventh TFT is connected to the third power source, and a drain of the seventh TFT is connected to the first node;

a first terminal of the second capacitor is connected to the first clock signal terminal; and

a second clock signal input via the second clock signal terminal is opposite to a first clock signal input via the first clock signal terminal in phase.

15. The shift register according to claim 14, wherein, the second power source supplies a second power signal whose voltage is VGL, the third power source supplies a third power signal whose voltage is VGL1, the fifth power source supplies a fifth power signal whose voltage is VGL2, and VGL2≦

VGL1≦

VGL.

16. A gate driving circuit, comprising multiple stages of shift registers, each of which is the shift register according to claim 1, wherein the output terminal of each of the shift registers is connected to the reset signal input terminal of a shift register in a previous stage and the start signal input terminal of a shift register in a next stage.

17. The gate driving circuit according to claim 16, wherein the second power source supplies a second power signal whose voltage is VGL, the third power source supplies a third power signal whose voltage is VGL1, and VGL1≦

VGL.

18. The gate driving circuit according to claim 16, wherein

the second terminal of the third capacitor is also connected to the output terminal of the shift register, the start signal input terminal of a previous stage shift register, or the start signal input terminal of a next stage shift register.

19. A display device, comprising the gate driving circuit according to claim 16.