Method for manufacturing thin film semiconductor device

• US 9,627,198 B2
• Filed: 09/30/2010
• Issued: 04/18/2017
• Est. Priority Date: 10/05/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Miyanaga, Akiharu, Takahashi, Masahiro, Kishida, Hideyuki, Sakata, Junichiro
• Primary Examiner(s): Hu, Shouxiang
• Application Number:
  US12/894,791
• Publication Number:
  US 20110079778A1
• Time in Patent Office: 2,392 Days
• Field of Search: 438104, 438149, 438158, 257E2146
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02172 the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides materials containing silicon H01L21/02123; metal silicates H01L21/02142
• CPC Class Codes: H01L 21/02266 deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
• CPC Class Codes: H01L 21/02422 Non-crystalline insulating materials, e.g. glass, polymers
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs

Abstract

An object is to provide a semiconductor device with stable electric characteristics in which an oxide semiconductor is used. The impurity concentration in the oxide semiconductor layer is reduced in the following manner: a silicon oxide layer including many defects typified by dangling bonds is formed in contact with the oxide semiconductor layer, and an impurity such as hydrogen or moisture (a hydrogen atom or a compound including a hydrogen atom such as H₂O) included in the oxide semiconductor layer is diffused into the silicon oxide layer. Further, a mixed region is provided between the oxide semiconductor layer and the silicon oxide layer. The mixed region includes oxygen, silicon, and at least one kind of metal element that is included in the oxide semiconductor.

Claims

1. A manufacturing method of a semiconductor device comprising steps of:

forming a gate electrode layer over a substrate,

forming a gate insulating layer over the gate electrode layer;

introducing the substrate into a first treatment chamber;

performing a first sputtering operation using an oxide semiconductor target to form an oxide semiconductor layer over the gate insulating layer;

heating the substrate, the gate insulating layer, and the oxide semiconductor layer at a temperature higher than or equal to 100°

C. and lower than or equal to 400°

C. after performing the first sputtering operation; and

forming, over and in contact with the oxide semiconductor layer, a silicon oxide layer including defects at a temperature higher than or equal to 0°

C. and lower than or equal to 50°

C. after the step of heating the substrate the gate insulating layer, and the oxide semiconductor layer,

wherein the substrate is heated during the step of forming of the oxide semiconductor layer at a first temperature.

2. The manufacturing method of a semiconductor device according to claim 1, wherein the oxide semiconductor layer includes at least one of indium, gallium, and zinc.

3. The manufacturing method of a semiconductor device according to claim 1,

wherein a mixed region having a thickness comprised between 1 nm and 10 nm is provided at an interface between the oxide semiconductor layer and the silicon oxide layer,

wherein the mixed region includes oxygen, silicon, and at least one kind of metal element included in the oxide semiconductor layer.

4. The manufacturing method of a semiconductor device according to claim 1,

wherein the silicon oxide layer is formed by performing a second sputtering operation.

5. The manufacturing method of a semiconductor device according to claim 1, wherein a filling rate of the oxide semiconductor target is greater than or equal to 90%.

6. The manufacturing method of a semiconductor device according to claim 1,

wherein the step of heating the substrate, the gate insulating layer, and the oxide semiconductor layer is performed in a second chamber, and

wherein the step of forming the silicon oxide layer is performed in a third chamber.

7. The manufacturing method of a semiconductor device according to claim 1, wherein the silicon oxide layer is in contact with the gate insulating layer.

8. A manufacturing method of a semiconductor device comprising steps of:

forming a gate electrode layer over a substrate,

forming a gate insulating layer over the gate electrode layer;

introducing the substrate into a first treatment chamber;

introducing into the first treatment chamber an oxygen gas and a rare gas, wherein each of the oxygen gas and the rare gas has a purity of 7N or higher;

performing a first sputtering operation using an oxide semiconductor target to form an oxide semiconductor layer having hydrogen concentration of 2×

10¹⁹ cm<sup>−

3</sup> or less when measured by secondary ion mass spectrometry, over the gate insulating layer;

heating the substrate, the gate insulating layer, and the oxide semiconductor layer at a temperature higher than or equal to 100°

C. and lower than or equal to 400°

C. after performing the first sputtering operation; and

then forming, over the oxide semiconductor layer, a silicon oxide layer including defects at a temperature higher than or equal to 0°

C. and lower than or equal to 50°

C.,

wherein the substrate is heated during the step of forming of the oxide semiconductor layer at a first temperature.

9. The manufacturing method of a semiconductor device according to claim 8, wherein the oxide semiconductor layer includes at least one of indium, gallium, and zinc.

10. The manufacturing method of a semiconductor device according to claim 8,

wherein a mixed region having a thickness comprised between 1 nm and 10 nm is provided at an interface between the oxide semiconductor layer and the silicon oxide layer,

wherein the mixed region includes oxygen, silicon, and at least one kind of metal element included in the oxide semiconductor layer.

11. The manufacturing method of a semiconductor device according to claim 8,

wherein the silicon oxide layer is formed by performing a second sputtering operation.

12. The manufacturing method of a semiconductor device according to claim 8, wherein a filling rate of the oxide semiconductor target is greater than or equal to 90%.

13. The manufacturing method of a semiconductor device according to claim 8,

wherein the step of heating the substrate, the gate insulating layer, and the oxide semiconductor layer is performed in a second chamber, and

wherein the step of forming the silicon oxide layer is performed in a third chamber.

14. The manufacturing method of a semiconductor device according to claim 8, wherein the silicon oxide layer is in contact with the gate insulating layer.