Methods and systems for dopant activation using microwave radiation

• US 9,627,212 B2
• Filed: 07/22/2016
• Issued: 04/18/2017
• Est. Priority Date: 08/09/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tsai, Chun-Hsiung, Yang, Huai-Tei, Yu, Kuo-Feng, Chen, Kei-Wei
• Primary Examiner(s): Potter, Roy
• Assistant Examiner(s): PATTON, PAUL E
• Application Number:
  US15/217,024
• Publication Number:
  US 20160329212A1
• Time in Patent Office: 270 Days
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02584 Delta-doping
• CPC Class Codes: H01L 21/02694 Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
• CPC Class Codes: H01L 21/2252 using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
• CPC Class Codes: H01L 21/2254 from or through or into an applied layer, e.g. photoresist, nitrides
• CPC Class Codes: H01L 21/2686 using incoherent radiation
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/67115 mainly by radiation
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/32 the imperfections being within the semiconductor body
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H05B 6/80 Apparatus for specific applications stoves or ranges F24C7/02

Abstract

A semiconductor structure includes a substrate, a source/drain (S/D) junction, and an S/D contact. The S/D junction is associated with the substrate and includes a trench-defining wall, a semiconductor layer, and a semiconductor material. The trench-defining wall defines a trench. The semiconductor layer is formed over the trench-defining wall, partially fills the trench, substantially covers the trench-defining wall, and includes germanium. The semiconductor material is formed over the semiconductor layer and includes germanium, a percentage composition of which is greater than a percentage composition of the germanium of the semiconductor layer. The S/D contact is formed over the S/D junction.

Claims

1. A semiconductor structure comprising:

a substrate;

a source/drain (S/D) junction associated with the substrate and including

a trench-defining wall that defines a trench,

a semiconductor layer that is formed over the trench-defining wall, that partially fills the trench, that substantially covers the trench-defining wall, and that includes germanium, and

a semiconductor material that is formed over the semiconductor layer and that includes germanium, a percentage composition of which is greater than a percentage composition of the germanium of the semiconductor layer; and

an S/D contact formed over the S/D junction.

2. The semiconductor structure of claim 1, wherein the semiconductor material substantially fills the trench.

3. The semiconductor structure of claim 1, wherein the semiconductor layer includes boron, a concentration of which is greater than a concentration of boron of the semiconductor material.

4. The semiconductor structure of claim 1, wherein the semiconductor layer includes a plurality of sublayers and a percentage composition of germanium of an innermost sublayer of the sublayers is greater than a percentage composition of germanium of an outermost sublayer of the sublayers.

5. The semiconductor structure of claim 1, wherein the S/D contact and the S/D junction have a contact resistivity therebetween of less than about 5E-9 Ohms-cm².

6. A semiconductor structure comprising:

a substrate; and

a source/drain (S/D) junction associated with the substrate and including

a trench-defining wall,

a semiconductor layer that is formed over the trench-defining wall and that has a plurality of sublayers, wherein a concentration of boron of an outermost sublayer of the sublayers is greater than a concentration of boron of an innermost sublayer of the sublayers, and

a semiconductor material that is formed over the semiconductor layer; and

an S/D contact formed over the S/D junction.

7. The semiconductor structure of claim 6, wherein the trench-defining wall defines a trench, the semiconductor layer partially fills the trench, and the semiconductor material substantially fills the trench.

8. The semiconductor structure of claim 6, wherein the semiconductor material includes germanium, a percentage composition of which is greater than a percentage composition of germanium of the semiconductor layer.

9. The semiconductor structure of claim 6, wherein a percentage composition of germanium of the innermost sublayer is greater than a percentage composition of germanium of the outermost sublayer.

10. The semiconductor structure of claim 6, wherein the S/D contact and the S/D junction have a contact resistivity therebetween of less than about 5E-9 Ohms-cm².

11. A method comprising:

providing a semiconductor structure that includes a substrate;

forming a source/drain (S/D) junction includes

forming in the substrate a trench that is defined by a trench-defining wall,

forming over the trench-defining wall a semiconductor layer that partially fills the trench, that substantially covers the trench-defining wall, and that includes germanium, and

forming over the semiconductor layer a semiconductor material that includes germanium, a percentage composition of which is greater than a percentage composition of the germanium of the semiconductor layer; and

forming an S/D contact over the S/D junction.

12. The method of claim 11, wherein forming the semiconductor material is such that the semiconductor material substantially fills the trench.

13. The method of claim 11, wherein forming the semiconductor layer is such that the semiconductor layer includes boron, a concentration of which is greater than a concentration of boron of the semiconductor material.

14. The method of claim 11, wherein forming the semiconductor layer is such that the semiconductor layer includes a plurality of sublayers and such that a percentage composition of germanium of an innermost sublayer of the sublayers is greater than a percentage composition of germanium of an outermost sublayer of the sublayers.

15. The method of claim 11, wherein forming the semiconductor layer is such that the semiconductor layer includes a plurality of sublayers and such that a concentration of boron of an outermost sublayer of the sublayers is greater than a concentration of boron of an innermost sublayer of the sublayers.

16. The method of claim 11, wherein forming the S/D junction and forming the S/D contact are such that a contact resistivity between the S/D junction and the S/D contact is less than about 5E-9 Ohms-cm².

17. The method of claim 11, wherein forming the semiconductor material is such that a crystal defect density of the germanium thereof is less than about 1E12 atoms/cm³.

18. The method of claim 11, further comprising activating dopant of the semiconductor structure by applying microwave radiation to a microwave-absorption material and the semiconductor structure, the microwave-absorption material being configured to increase absorption of the microwave radiation by the dopant of the semiconductor structure.

19. The method of claim 18, wherein activating the dopant further includes:

forming the microwave-absorption material over the semiconductor structure; and

adjusting a thickness of the microwave-absorption material.

20. The method of claim 18, wherein activating the dopant further includes:

receiving the microwave-absorption material; and

adjusting the microwave-absorption material at a distance from the semiconductor structure.