Apparatus and method for power MOS transistor

• US 9,627,265 B2
• Filed: 03/21/2016
• Issued: 04/18/2017
• Est. Priority Date: 07/11/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Su, Po-Chih, Chou, Hsueh-Liang, Ng, Chun-Wai, Liu, Ruey-Hsin
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): Jiang, Fang-Xing
• Application Number:
  US15/075,882
• Publication Number:
  US 20160204227A1
• Time in Patent Office: 393 Days
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/2815 part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/781 Inverted VDMOS transistors, i.e. Source-Down VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A method comprises providing a substrate with a second conductivity type, growing a first epitaxial layer having the second conductivity type, growing a second epitaxial layer having a first conductivity type, forming a trench in the first epitaxial layer and the second epitaxial layer, forming a gate electrode in the trench, applying an ion implantation process using first gate electrode as an ion implantation mask to form a drain-drift region, forming a field plate in the trench, forming a drain region in the second epitaxial layer, wherein the drain region has the first conductivity type and forming a source region in the first epitaxial layer, wherein the source region has the first conductivity type, and wherein the source region is electrically coupled to the field plate.

Claims

1. A method comprising:

growing a first epitaxial layer over a substrate;

growing a second epitaxial layer over the first epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer have different conductivity types;

forming a first trench extending through the second epitaxial layer and partially through the first epitaxial layer;

depositing a gate dielectric layer on sidewalls and a bottom of the first trench;

depositing a gate electrode layer over the gate dielectric layer;

applying a first etching process to the gate electrode layer, wherein as a result of performing the step of applying the first etching process to the gate electrode layer, a top surface of the first epitaxial layer is higher than a top surface of the gate electrode layer;

forming a source region underneath a center portion of the bottom of the first trench;

applying a second etching process to the gate dielectric layer until the source region is exposed;

forming a second trench by removing a center portion of the source region, wherein the second trench extend through the source region and partially through the first epitaxial layer;

forming a doped region having a first portion in the first epitaxial layer and a second portion in the substrate; and

forming a field plate having a lower portion in the second trench and an upper portion in the first trench.

2. The method of claim 1, wherein:

the substrate is a p-type substrate;

the first epitaxial layer is a p-type epitaxial layer; and

the second epitaxial layer is an n-type epitaxial layer.

3. The method of claim 1, further comprising:

forming a drain-drift region in the first epitaxial layer, wherein;

the drain-drift region is formed along the sidewalls of the first trench; and

a bottom portion of the drain-drift region is approximately aligned with an upper portion of the gate electrode layer.

4. The method of claim 1, further comprising:

forming the source region through an ion implantation process.

5. The method of claim 1, further comprising:

forming a drain-drift region through a tilted angle ion implantation process, wherein the gate electrode layer is used as an ion implantation mask.

6. The method of claim 1, further comprising:

before the step of applying the second etching process to the gate dielectric layer, forming a dielectric layer over the gate electrode layer.

7. The method of claim 1, further comprising:

forming a drain region in the second epitaxial layer, wherein a bottom surface of the drain region is higher than a top surface of the field plate.

8. The method of claim 1, further comprising:

depositing an oxide layer over the field plate, wherein a bottom surface of the oxide layer is higher than a bottom surface of the second epitaxial layer.

9. The method of claim 1, further comprising:

depositing a conductive material in the first trench and the second trench; and

removing an upper portion of the conductive material to form the field plate.

10. A method comprising:

growing a p-type epitaxial layer over a p-type substrate;

growing an n-type epitaxial layer over the p-type epitaxial layer;

forming a first trench in the n-type epitaxial layer and the p-type epitaxial layer, wherein a bottom surface of the first trench is higher than a top surface of the p-type substrate;

depositing a gate electrode layer on sidewalls and a bottom of the first trench;

forming a source region underneath a center portion of the bottom of the first trench, wherein a bottom surface of the source region is higher than the top surface of the p-type substrate;

forming a second trench, wherein the second trench extends through the source region and partially through the p-type epitaxial layer;

forming a doped region underneath the source region, wherein the doped region has a first portion in the p-type epitaxial layer and a second portion in the p-type substrate;

forming a field plate having a lower portion in the second trench and an upper portion in the first trench; and

forming a drain region in the n-type epitaxial layer, wherein a bottom surface of the drain region is higher than a top surface of the field plate.

11. The method of claim 10, further comprising:

before the step of depositing the gate electrode layer, depositing a gate dielectric layer on the sidewalls and the bottom of the first trench.

12. The method of claim 11, further comprising:

forming the second trench by performing a first etching process; and

applying a second etching process to the gate electrode layer, wherein as a result of performing the step of applying the second etching process to the gate electrode layer, a top surface of the p-type epitaxial layer is higher than a top surface of the gate electrode layer and a portion of the gate dielectric layer on the bottom of the first trench is exposed.

13. The method of claim 10, further comprising:

forming a drain-drift region, wherein a bottom portion of the drain-drift region is approximately aligned with an upper portion of the gate electrode layer.

14. The method of claim 13, further comprising:

forming the drain-drift region through a tilted angle ion implantation process.

15. A method comprising:

providing a substrate with a second conductivity type;

growing a first epitaxial layer having the second conductivity type;

growing a second epitaxial layer having a first conductivity type;

forming a trench in the first epitaxial layer and the second epitaxial layer;

forming a gate electrode in the trench;

applying an ion implantation process to form a drain-drift region;

forming a field plate in the trench;

forming a drain region in the second epitaxial layer, wherein the drain region has the first conductivity type; and

forming a source region in the first epitaxial layer, wherein the source region has the first conductivity type, and wherein the source region is electrically coupled to the field plate.

16. The method of claim 15, further comprising:

forming the drain-drift region along sidewalls of the trench, wherein an upper portion of the gate electrode is aligned with a bottom portion of the drain-drift region.

17. The method of claim 15, further comprising:

filling free space between the field plate and the gate electrode with a dielectric material.

18. The method of claim 17, further comprising:

the dielectric material is oxide.

19. The method of claim 15, further comprising:

forming a drain contact plug coupled to the drain region, wherein the drain contact plug is formed over a first side of the substrate; and

forming a source contact plug coupled to the source region, wherein the source contact plug is formed over a second side of the substrate.

20. The method of claim 19, further comprising:

forming a p+ region in the first epitaxial layer, wherein the source region is coupled to the source contact plug through the field plate, the p+ region and the substrate.