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Apparatus and method for power MOS transistor

  • US 9,627,265 B2
  • Filed: 03/21/2016
  • Issued: 04/18/2017
  • Est. Priority Date: 07/11/2012
  • Status: Active Grant
First Claim
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1. A method comprising:

  • growing a first epitaxial layer over a substrate;

    growing a second epitaxial layer over the first epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer have different conductivity types;

    forming a first trench extending through the second epitaxial layer and partially through the first epitaxial layer;

    depositing a gate dielectric layer on sidewalls and a bottom of the first trench;

    depositing a gate electrode layer over the gate dielectric layer;

    applying a first etching process to the gate electrode layer, wherein as a result of performing the step of applying the first etching process to the gate electrode layer, a top surface of the first epitaxial layer is higher than a top surface of the gate electrode layer;

    forming a source region underneath a center portion of the bottom of the first trench;

    applying a second etching process to the gate dielectric layer until the source region is exposed;

    forming a second trench by removing a center portion of the source region, wherein the second trench extend through the source region and partially through the first epitaxial layer;

    forming a doped region having a first portion in the first epitaxial layer and a second portion in the substrate; and

    forming a field plate having a lower portion in the second trench and an upper portion in the first trench.

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