Method and structure for enabling controlled spacer RIE

• US 9,627,277 B2
• Filed: 06/09/2015
• Issued: 04/18/2017
• Est. Priority Date: 06/09/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Jung, Ryan O., Lie, Fee Li, Miller, Eric R., Shearer, Jeffrey C., Sporre, John R., Teehan, Sean
• Primary Examiner(s): Armand, Marc
• Assistant Examiner(s): TANG, SUIAN
• Application Number:
  US14/734,615
• Publication Number:
  US 20160365292A1
• Time in Patent Office: 679 Days
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31051 Planarisation of the insulating layers H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 22/26 Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement endpoint detection arrangements in CMP apparatus B24B37/013, in discharge apparatus H01J37/32
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability

Abstract

A method and structure to enable reliable dielectric spacer endpoint detection by utilizing a sacrificial spacer fin are provided. The sacrificial spacer fin that is employed has a same pitch as the pitch of each semiconductor fin and the same height as the dielectric spacers on the sidewalls of each semiconductor fin. Exposed portions of the sacrificial spacer fin are removed simultaneously during a dielectric spacer reactive ion etch (RIE). The presence of the sacrificial spacer fin improves the endpoint detection of the spacer RIE and increases the endpoint signal intensity.

Claims

1. A method of forming a semiconductor structure, said method comprising:

providing a plurality of semiconductor fins extending upwards from a surface of a substrate, and a plurality of sacrificial spacer fins extending upwards from another surface of said substrate;

forming a sacrificial gate structure straddling over a portion of each semiconductor fin and each sacrificial spacer fin;

forming a dielectric spacer material surrounding said sacrificial gate structure, wherein said dielectric spacer material and each sacrificial spacer fin comprise a same dielectric material; and

performing a spacer reactive ion etch to said dielectric spacer material to provide a dielectric spacer on sidewall surfaces of said sacrificial gate structure, wherein during said spacer reactive ion etch exposed portions of each sacrificial spacer fin are removed, while maintaining a portion of each sacrificial spacer fin beneath said dielectric spacer and said sacrificial gate structure.

2. The method of claim 1, wherein each of said plurality of semiconductor fins has a height and width that is the same as each sacrificial spacer fin.

3. The method of claim 1, wherein said providing said plurality of semiconductor fins comprises:

forming a first set of semiconductor fins on said surface of said substrate and a set second of semiconductor fins on said another surface of said substrate; and

replacing each semiconductor fin of said second set of semiconductor fins with a sacrificial spacer material.

4. The method of claim 3, wherein said forming said first set of semiconductor fins and said second set of semiconductor fins comprises:

providing a semiconductor-on-insulator substrate comprising, from bottom to top, a handle substrate, an insulator layer and a semiconductor material layer; and

patterning said semiconductor material layer utilizing a sidewall image transfer process or lithography and etching.

5. The method of claim 3, wherein said replacing each semiconductor fin of said second set of semiconductor fins with said sacrificial spacer material comprises:

forming a protective dielectric liner on surfaces of said first set of semiconductor fins and said set second of semiconductor fins;

forming a sacrificial dielectric material on said protective dielectric liner and atop each semiconductor fin of said first and second sets of semiconductor fins;

planarizing said sacrificial dielectric material and said protective dielectric liner to provide a sacrificial dielectric material portion within a U-shaped protective dielectric liner portion, wherein each U-shaped protective dielectric liner portion and each sacrificial dielectric material portion have a topmost surface that is coplanar with a topmost surface of each semiconductor fin of said first and second sets of semiconductor fins;

forming a block mask structure of said first set of semiconductor fins;

removing each semiconductor fin of said second set of semiconductor fins; and

providing said sacrificial spacer material within a volume previously occupied by each semiconductor fin of said second set of semiconductor fins.

6. The method of claim 1, wherein said forming said sacrificial gate structure comprises:

forming a protective dielectric liner on exposed surfaces of each semiconductor fin and each sacrificial spacer fin;

forming a sacrificial gate material on said protective dielectric liner and atop each semiconductor fin and each sacrificial spacer fin;

forming a hard mask stack on said sacrificial gate material; and

patterning at least said hard mask stack and said sacrificial gate material by lithography and etching.

7. The method of claim 1, wherein during said spacer reactive ion etch each sacrificial spacer fin provides an increased endpoint detection signal.

8. The method of claim 1, wherein said dielectric spacer material and each sacrificial spacer fin comprise silicon nitride.

9. The method of claim 1, further comprising replacing the sacrificial gate structure with a functional gate structure.

10. The method of claim 1, wherein each sacrificial spacer fin is present in a Kerf region of said substrate.