Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and AA-short-configured, NCEM-enabled fill cells
First Claim
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1. A monolithic integrated circuit (IC) that includes at least a source/drain (AA) layer, a source/drain contact (AACNT) layer, a source/drain silicide (TS) layer, a gate (GATE) layer, a gate contact (GATECNT) layer, a via to interconnect stack (V0) layer, a first wiring (M1) layer, a second wiring (M2) layer, and an M1-to-M2 via (V1) layer, said IC comprising at least:
- (i) a plurality of logic cells selected from a standard cell library in which each logic cell has a height, supply rail configuration, and GATE pitch (CPP) configured for abutted instantiation with other logic cells in the library; and
,(ii) a plurality of at least four different, non-contact electrical measurement (NCEM)-enabled fill cells, each of said NCEM-enabled fill cells having a height, supply rail configuration, and CPP configured for abutted instantiation with logic cells in the standard cell library, said plurality of NCEM-enabled fill cells including;
(a) at least one via-open-configured, NCEM-enabled fill cell that includes standard patterning consistent with cells in the standard cell library and test area patterning configured to enable NCEM detection of at least one unintended open circuit condition that relates to via patterning;
(b) at least one GATE-short-configured, NCEM-enabled fill cell that includes standard patterning consistent with cells in the standard cell library and test gap patterning configured to enable NCEM detection of at least one unintended short circuit condition that relates to GATE patterning;
(c) at least one GATECNT-short-configured, NCEM-enabled fill cell that includes standard patterning consistent with cells in the standard cell library and test gap patterning configured to enable NCEM detection of at least one unintended short circuit condition that relates to GATECNT patterning; and
,(d) at least one AA-short-configured, NCEM-enabled fill cell that includes standard patterning consistent with cells in the standard cell library and test gap patterning configured to enable NCEM detection of at least one unintended short circuit condition that relates to AA patterning.
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Abstract
An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of open-circuit and short-circuit failure modes, including at least one via-open-related failure mode, one GATE-short-related failure mode, one GATECNT-short-related failure mode, and one AA-short-related failure mode.
103 Citations
20 Claims
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1. A monolithic integrated circuit (IC) that includes at least a source/drain (AA) layer, a source/drain contact (AACNT) layer, a source/drain silicide (TS) layer, a gate (GATE) layer, a gate contact (GATECNT) layer, a via to interconnect stack (V0) layer, a first wiring (M1) layer, a second wiring (M2) layer, and an M1-to-M2 via (V1) layer, said IC comprising at least:
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(i) a plurality of logic cells selected from a standard cell library in which each logic cell has a height, supply rail configuration, and GATE pitch (CPP) configured for abutted instantiation with other logic cells in the library; and
,(ii) a plurality of at least four different, non-contact electrical measurement (NCEM)-enabled fill cells, each of said NCEM-enabled fill cells having a height, supply rail configuration, and CPP configured for abutted instantiation with logic cells in the standard cell library, said plurality of NCEM-enabled fill cells including; (a) at least one via-open-configured, NCEM-enabled fill cell that includes standard patterning consistent with cells in the standard cell library and test area patterning configured to enable NCEM detection of at least one unintended open circuit condition that relates to via patterning; (b) at least one GATE-short-configured, NCEM-enabled fill cell that includes standard patterning consistent with cells in the standard cell library and test gap patterning configured to enable NCEM detection of at least one unintended short circuit condition that relates to GATE patterning; (c) at least one GATECNT-short-configured, NCEM-enabled fill cell that includes standard patterning consistent with cells in the standard cell library and test gap patterning configured to enable NCEM detection of at least one unintended short circuit condition that relates to GATECNT patterning; and
,(d) at least one AA-short-configured, NCEM-enabled fill cell that includes standard patterning consistent with cells in the standard cell library and test gap patterning configured to enable NCEM detection of at least one unintended short circuit condition that relates to AA patterning. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification
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InventorsBrozek, Tomasz, Cheng, Jeremy, Comensoli, Simone, Doong, Kelvin, Fiscus, Timothy, Lee, Sherry, Liao, Marci, Lin, Sheng-Che, Matsuhashi, Hideki, Michaels, Kimon, Rauscher, Markus, Rovner, Vyacheslav, Strojwas, Marcin, Vallishayee, Rakesh, Weiland, Larg, Yokoyama, Nobuharu, Lam, Stephen, Ciplickas, Dennis, De, Indranil, Eisenmann, Hans, Haigh, Jonathan, Hess, Christopher, Kibarian, John, O'Sullivan, Conor, Strojwas, Andrzej, Taylor, Carl
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Primary Examiner(s)Dinh, Paul
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Application NumberUS15/391,018Time in Patent Office112 DaysField of Search716 52, 716 54, 716 55, 716100, 716110, 716112US Class CurrentCPC Class CodesG06F 11/079 Root cause analysis, i.e. e...G06F 30/30 Circuit designG06F 30/39 Circuit design at the physi...G06F 30/392 Floor-planning or layout, e...G06F 30/398 Design verification or opti...H01L 21/823437 with a particular manufactu...H01L 21/823475 interconnection or wiring o...H01L 22/20 Sequence of activities cons...H01L 22/26 Acting in response to an on...H01L 22/32 Additional lead-in metallis...H01L 22/34 Circuits for electrically c...H01L 23/5226 Via connections in a multil...H01L 23/528 Geometry or layout of the i...H01L 27/0207 Geometrical layout of the c...H01L 27/088 the components being field-...H01L 27/092 complementary MIS field-eff...H01L 29/0649 Dielectric regions, e.g. Si...H01L 29/0684 characterised by the shape,...H01L 29/41725 Source or drain electrodes ...H01L 29/45 Ohmic electrodes
