Methods of forming FINFETs with locally thinned channels from fins having in-situ doped epitaxial cladding
First Claim
1. A method of forming fin field-effect transistor (FET) devices, the method comprising the steps of:
- patterning fins in a wafer;
forming a doped epitaxial cladding layer on the fins prior to forming dummy gates, wherein the doped epitaxial cladding layer is in-situ doped with an n-type or a p-type dopant;
forming the dummy gates over portions of the fins that serve as channel regions of the finFET device;
forming spacers on opposite sides of the dummy gates;
depositing a gap fill oxide on the wafer, filling any gaps between the spacers;
removing the dummy gates forming gate trenches;
trimming the fins within the gate trenches such that a width of the fins within the gate trenches is less than the width of the fins under the spacers adjacent to the gate trenches, wherein u-shaped grooves are formed in sides of the fins within the gate trenches; and
forming replacement gate stacks in the gate trenches over the portions of the fins that serve as the channel regions of the finFET devices, wherein portions of the fins adjacent to the replacement gate stacks serve as source and drain regions of the finFET devices.
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Abstract
In one aspect, a method of forming finFET devices is provided which includes patterning fins in a wafer; forming dummy gates over the fins; forming spacers on opposite sides of the dummy gates; depositing a gap fill oxide on the wafer, filling any gaps between the spacers; removing the dummy gates forming gate trenches; trimming the fins within the gate trenches such that a width of the fins within the gate trenches is less than the width of the fins under the spacers adjacent to the gate trenches, wherein u-shaped grooves are formed in sides of the fins within the gate trenches; and forming replacement gate stacks in the gate trenches, wherein portions of the fins adjacent to the replacement gate stacks serve as source and drain regions of the finFET devices.
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Citations
15 Claims
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1. A method of forming fin field-effect transistor (FET) devices, the method comprising the steps of:
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patterning fins in a wafer; forming a doped epitaxial cladding layer on the fins prior to forming dummy gates, wherein the doped epitaxial cladding layer is in-situ doped with an n-type or a p-type dopant; forming the dummy gates over portions of the fins that serve as channel regions of the finFET device; forming spacers on opposite sides of the dummy gates; depositing a gap fill oxide on the wafer, filling any gaps between the spacers; removing the dummy gates forming gate trenches; trimming the fins within the gate trenches such that a width of the fins within the gate trenches is less than the width of the fins under the spacers adjacent to the gate trenches, wherein u-shaped grooves are formed in sides of the fins within the gate trenches; and forming replacement gate stacks in the gate trenches over the portions of the fins that serve as the channel regions of the finFET devices, wherein portions of the fins adjacent to the replacement gate stacks serve as source and drain regions of the finFET devices. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method of forming fin FET devices, the method comprising the steps of:
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patterning fins in a wafer using a fin hardmask; forming a doped epitaxial cladding layer on the fins prior to forming dummy gates, wherein the doped epitaxial cladding layer is in-situ doped with an n-type or a p-type dopant; forming the dummy gates over portions of the fins that serve as channel regions of the finFET device; forming spacers on opposite sides of the dummy gates; depositing a gap fill oxide on the wafer, filling any gaps between the spacers; removing the dummy gates forming gate trenches; trimming the fin hardmask to a width smaller than a patterned width of the fins prior to trimming the fins; trimming the fins within the gate trenches such that a width of the fins within the gate trenches is less than the width of the fins under the spacers adjacent to the gate trenches, wherein u-shaped grooves are formed in sides of the fins within the gate trenches; removing the fin hardmask after trimming the fins; and forming replacement gate stacks in the gate trenches over the portions of the fins that serve as the channel regions of the finFET devices, wherein portions of the fins adjacent to the replacement gate stacks serve as source and drain regions of the finFET devices.
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Specification