CMOS NFET and PFET comparable spacer width

• US 9,627,382 B2
• Filed: 03/24/2016
• Issued: 04/18/2017
• Est. Priority Date: 02/16/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Ok, Injo, Seo, Soon-Cheon
• Primary Examiner(s): ULLAH, ELIAS
• Application Number:
  US15/079,613
• Publication Number:
  US 20160240535A1
• Time in Patent Office: 390 Days
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled

Abstract

Embodiments of the present disclosure provide a structure including: a p-type field effect transistor (pFET device) and an n-type field effect transistor (nFET device) each having sidewall spacers on opposite sidewalls of a gate and source drain region adjacent to the sidewall spacers, a distance between the pFET source drain region and the pFET gate is substantially equal to a distance between the nFET source drain region and the nFET gate.

Claims

1. A structure comprising:

a p-type field effect transistor (pFET device) and an n-type field effect transistor (nFET device) each having sidewall spacers on opposite sidewalls of a gate, wherein the sidewall spacers of the pFET device are of substantially equal lateral thickness to the sidewall spacers of the nFET device; and

a source drain region adjacent to the sidewall spacers, a distance between the pFET source drain region and the pFET gate is substantially equal to a distance between the nFET source drain region and the nFET gate.

2. The structure of claim 1, further comprising:

a first liner above and in direct contact with the pFET sidewall spacers and the pFET source drain region; and

a second liner above and in direct contact with the nFET sidewall spacers and the NFET source drain region, such that substantially vertical portions of the first liner and the second liner are in direct contact with each other; and

wherein the substantially vertical portion of the first liner and the substantially vertical portion of the second liner are located between the pFET device and the nFET device, and are in direct contact with one another.

3. The structure of claim 1 wherein the first liner comprises silicon.

4. The structure of claim 1, wherein the first liner comprises a metal.

5. A structure comprising:

a p-type field effect transistor (pFET device) including a dummy gate and a pair of sidewall spacers each laterally adjacent to opposing sidewalls thereof; and

an n-type field effect transistor (nFET device) including a dummy gate and pair of sidewall spacers each laterally adjacent to opposing sidewalls thereof, wherein the sidewall spacers of the pFET device are of substantially equal lateral thickness to the sidewall spacers of the nFET device, and wherein a lateral distance between a pFET source drain region adjacent to the sidewall spacers and the pFET dummy gate is substantially equal to a lateral distance between a nFET source drain region adjacent to the sidewall spacers and the nFET dummy gate.

6. The structure of claim 5, further comprising:

a first liner above and in direct contact with the pFET sidewall spacers and the pFET source drain region; and

a second liner above and in direct contact with the nFET sidewall spacers and the NFET source drain region, such that the first liner laterally abuts the second liner; and

wherein a substantially vertical portion of the first liner and a substantially vertical portion of the second liner are located between the pFET device and the nFET device, and are in direct contact with one another.

7. The structure of claim 5, wherein the first liner includes silicon.

8. The structure of claim 5, wherein the first liner includes a metal.

9. The structure of claim 5, wherein the dummy gate includes polysilicon.

10. The structure of claim 5, wherein the dummy gate comprises a metal.