Tuning tensile strain on FinFET

• US 9,627,385 B2
• Filed: 08/28/2015
• Issued: 04/18/2017
• Est. Priority Date: 05/23/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng, Lin, Zhi-Chang, Chen, Guan-Lin, Hsu, Ting-Hung, Huang, Jiun-Jia
• Primary Examiner(s): PARENDO, KEVIN A
• Application Number:
  US14/839,560
• Publication Number:
  US 20160056157A1
• Time in Patent Office: 599 Days
• CPC Class Codes: H01L 21/02356 treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A fin field effect transistor (FinFET) having a tunable tensile strain and an embodiment method of tuning tensile strain in an integrated circuit are provided. The method includes forming a source/drain region on opposing sides of a gate region in a fin, forming spacers over the fin, the spacers adjacent to the source/drain regions, depositing a dielectric between the spacers; and performing an annealing process to contract the dielectric, the dielectric contraction deforming the spacers, the spacer deformation enlarging the gate region in the fin.

Claims

1. A semiconductor device comprising

a first device of a first conductivity type, the first device having a first gate electrode, first sidewalls of the first gate electrode having a first profile;

and

a second device of a second conductivity type, the second device having a second gate electrode, second sidewalls of the second gate electrode having a second profile, the first profile different than the second profile, a first channel length of the first device being less than a second channel length of the second device, the first conductivity type being opposite the second conductivity type, the second sidewalls being adjacent a contracted dielectric, the contracted dielectric having a concave sidewall adjacent the second sidewalls.

2. The semiconductor device of claim 1, further comprising a first dielectric layer on opposing sides of the first gate electrode, wherein the first dielectric layer comprises a different material than the contracted dielectric.

3. The semiconductor device of claim 2, further comprising first spacers interposed between the first gate electrode and the first dielectric layer, and second spacers interposed between the second gate electrode and the contracted dielectric.

4. The semiconductor device of claim 1, wherein the first gate electrode comprises a first metal gate electrode and the second gate electrode comprises a second metal gate electrode.

5. The semiconductor device of claim 4, wherein the first gate electrode has a first height, the second gate electrode has a second height, the first height being different than the second height.

6. The semiconductor device of claim 1, wherein the first device is a p-type metal-oxide-semiconductor (PMOS) device and the second device is an n-type metal-oxide-semiconductor (NMOS).

7. The semiconductor device of claim 1, wherein the contracted dielectric has been reduced in size about 15% to about 18% relative to an original size of the contracted dielectric.

8. A semiconductor device comprising

a first device of a first conductivity type, the first device having a first gate electrode, the first gate electrode having a first dielectric layer on opposing sides thereof, first sidewalls of the first gate electrode having a first profile, the first profile having linear sidewalls;

and

a second device of a second conductivity type, the second device having a second gate electrode, the second gate electrode having a second dielectric layer on opposing sides thereof, second sidewalls of the second gate electrode having a second profile, the first profile different than the second profile, a first channel length of the first device being less than a second channel length of the second device, the second profile having convex sidewalls projecting toward the second dielectric layer, the second dielectric layer being a contracted dielectric layer having concave sidewalls, the first conductivity type being opposite the second conductivity type.

9. The semiconductor device of claim 8, wherein the first device is a p-type metal-oxide-semiconductor (PMOS) device, and the second device comprises an n-type metal-oxide-semiconductor (NMOS) device.

10. The semiconductor device of claim 8, further comprising a second spacer interposed between the second gate electrode and the second dielectric layer.

11. The semiconductor device of claim 10, further comprising a first spacer interposed between the first gate electrode and the first dielectric layer.

12. The semiconductor device of claim 8, wherein the first dielectric layer comprises a different material than the second dielectric layer.

13. The semiconductor device of claim 8, further comprising an interfacial oxide and a high-k dielectric interposed between a channel of the second device and the second gate electrode.

14. The semiconductor device of claim 8, wherein the second dielectric layer is more dense than the first dielectric layer.

15. The semiconductor device of claim 8, wherein the first gate electrode and the second gate electrode are different heights.

16. A semiconductor device comprising

a first device of a first conductivity type, the first device having a first gate electrode, first sidewalls of the first gate electrode having a first profile;

and

a second device of a second conductivity type, the second device having a second gate electrode and source/drain regions on opposing sides of the second gate electrode, the second device having a contracted dielectric disposed over the source/drain regions, the second device having spacers interposed between the second gate electrode and the contracted dielectric, second sidewalls of the second gate electrode having a second profile, the first profile different than the second profile, a first channel length of the first device being less than a second channel length of the second device, the first conductivity type being opposite the second conductivity type, the contracted dielectric having a concave sidewall facing toward the second gate electrode.

17. The semiconductor device of claim 16, wherein a contour of sidewalls of the contracted dielectric is equivalent to a contour of the spacers.

18. The semiconductor device of claim 16, wherein the contracted dielectric has been reduced in size about 15% to about 18% relative to an original size of the contracted dielectric.

19. The semiconductor device of claim 16, further comprising an interfacial oxide and a high-k dielectric interposed between a channel region of the second device and the second gate electrode.

20. The semiconductor device of claim 16, wherein the second gate electrode comprises a metal gate electrode.