Three dimensional memory arrays and stitching thereof

• US 9,627,438 B1
• Filed: 04/28/2016
• Issued: 04/18/2017
• Est. Priority Date: 04/28/2016
• Status: Active Grant

• Current Assignee: Avalanche Technology Incorporated
• Original Assignee: Avalanche Technology Incorporated
• Inventors: Satoh, Kimihiro, Yen, Bing K.
• Primary Examiner(s): Picardat, Kevin M
• Application Number:
  US15/141,726
• Time in Patent Office: 355 Days
• Field of Search: 257 5
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10B 61/10 comprising components having two electrodes, e.g. diodes or MIM elements
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/24 of the Ovonic threshold switching type
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/24 based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/882 Compounds of sulfur, selenium or tellurium, e.g. chalcogenides

Abstract

The present invention is directed to a memory device including a first layer of memory cells with each cell of the first layer of memory cells including a two-terminal selection element coupled to a memory element in series; a plurality of first local wiring lines connected to one ends of the first layer of memory cells along a first direction with each of the first local wiring lines being electrically connected to two first line selection transistors at two ends thereof; and a plurality of second local wiring lines connected to other ends of the first layer of memory cells along a second direction substantially orthogonal to the first direction with each of the second local wiring lines being electrically connected to two second line selection transistors at two ends thereof.

Claims

1. A memory device comprising:

a first layer of memory cells, each cell of said first layer of memory cells including a two-terminal selection element coupled to a memory element in series;

a plurality of first local wiring lines connected to one ends of said first layer of memory cells along a first direction, each of said first local wiring lines being electrically connected to two first line selection transistors at two ends thereof; and

a plurality of second local wiring lines connected to other ends of said first layer of memory cells along a second direction substantially orthogonal to said first direction, each of said second local wiring lines being electrically connected to two second line selection transistors at two ends thereof.

2. The memory device of claim 1 further comprising:

a plurality of first wiring lines extending along said first direction; and

a plurality of second wiring lines extending along said second direction,

wherein said two first line selection transistors at two ends of each of said first local wiring lines are further connected to one of said first wiring lines, said two second line selection transistors at two ends of each of said second local wiring lines are further connected to one of said second wiring lines.

3. The memory device of claim 2, wherein said first wiring lines are disposed beneath said first local wiring lines and said second wiring lines are disposed beneath said second local wiring lines.

4. The memory device of claim 2, wherein said first and second wiring lines each are split into two levels.

5. The memory device of claim 4, wherein said first and second wiring lines are substantially wider than said first and second local wiring lines.

6. The memory device of claim 4, wherein said first layer of memory cells are periodically arranged to have a pitch of P along said first and second directions, a width of said first and second wiring lines is greater than or equal to about P and less than about 2P.

7. The memory device of claim 1, wherein said two-terminal selection element is an Ovanic threshold switch.

8. The memory device of claim 1, wherein said two-terminal selection element is a diode.

9. The memory device of claim 1, wherein said memory element comprises a phase change chalcogenide compound.

10. The memory device of claim 1, wherein said memory element comprises a precipitate bridging metal oxide.

11. The memory device of claim 1, wherein said memory element comprises two magnetic layers with an insulating tunnel junction layer interposed therebetween.

12. The memory device of claim 1 further comprising:

a second layer of memory cells with one ends thereof coupled to said second local wiring lines, each cell of said second layer of memory cells including said two-terminal selection element coupled to said memory element in series; and

a plurality of third local wiring lines connected to other ends of said second layer of memory cells along said first direction, each of said third local wiring lines being electrically connected to two third line selection transistors at two ends thereof.

13. The memory device of claim 12 further comprising:

at least one more layer of memory cells with each cell including said two-terminal selection element coupled to said memory element in series; and

at least one more layer of a plurality of local wiring lines.

14. The memory device of claim 12, wherein said two-terminal selection element is an Ovanic threshold switch.

15. The memory device of claim 12, wherein said two-terminal selection element is disposed adjacent to a respective one of said second local wiring lines.

16. The memory device of claim 12, wherein said memory element comprises two magnetic layers with an insulating tunnel junction layer interposed therebetween.

17. The memory device of claim 12 further comprising:

a plurality of first wiring lines extending along said first direction; and

a plurality of second wiring lines extending along said second direction,

wherein said two first line selection transistors at two ends of each of said first local wiring lines are further connected to one of said first wiring lines, said two second line selection transistors at two ends of each of said second local wiring lines are further connected to one of said second wiring lines, said two third line selection transistors at two ends of each of said third local wiring lines are further connected to one of said first wiring lines.

18. The memory device of claim 17, wherein said first wiring lines are disposed beneath said first local wiring lines and said second wiring lines are disposed beneath said second local wiring lines.

19. The memory device of claim 17, wherein said first and second wiring lines each are split into two levels.

20. The memory device of claim 17, wherein said first and second wiring lines are substantially wider than said first, second, and third local wiring lines.

21. The memory device of claim 17, wherein said first and second layers of memory cells are periodically arranged to have a pitch of P along said first and second directions, a width of said first and second wiring lines is greater than or equal to about P and less than about 2P.