Three dimensional memory arrays and stitching thereof
First Claim
1. A memory device comprising:
- a first layer of memory cells, each cell of said first layer of memory cells including a two-terminal selection element coupled to a memory element in series;
a plurality of first local wiring lines connected to one ends of said first layer of memory cells along a first direction, each of said first local wiring lines being electrically connected to two first line selection transistors at two ends thereof; and
a plurality of second local wiring lines connected to other ends of said first layer of memory cells along a second direction substantially orthogonal to said first direction, each of said second local wiring lines being electrically connected to two second line selection transistors at two ends thereof.
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Accused Products
Abstract
The present invention is directed to a memory device including a first layer of memory cells with each cell of the first layer of memory cells including a two-terminal selection element coupled to a memory element in series; a plurality of first local wiring lines connected to one ends of the first layer of memory cells along a first direction with each of the first local wiring lines being electrically connected to two first line selection transistors at two ends thereof; and a plurality of second local wiring lines connected to other ends of the first layer of memory cells along a second direction substantially orthogonal to the first direction with each of the second local wiring lines being electrically connected to two second line selection transistors at two ends thereof.
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Citations
21 Claims
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1. A memory device comprising:
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a first layer of memory cells, each cell of said first layer of memory cells including a two-terminal selection element coupled to a memory element in series; a plurality of first local wiring lines connected to one ends of said first layer of memory cells along a first direction, each of said first local wiring lines being electrically connected to two first line selection transistors at two ends thereof; and a plurality of second local wiring lines connected to other ends of said first layer of memory cells along a second direction substantially orthogonal to said first direction, each of said second local wiring lines being electrically connected to two second line selection transistors at two ends thereof. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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Specification