Horizontally oriented and vertically stacked memory cells

• US 9,627,442 B2
• Filed: 04/26/2016
• Issued: 04/18/2017
• Est. Priority Date: 06/22/2010
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Quick, Timothy A., Marsh, Eugene P.
• Primary Examiner(s): Valentine, Jami M
• Application Number:
  US15/138,381
• Publication Number:
  US 20160240587A1
• Time in Patent Office: 357 Days
• Field of Search: 257 2- 5, 257E29002, 438102-104
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/026 by physical vapor deposition, e.g. sputtering
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/821 Device geometry
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/841 Electrodes
• CPC Class Codes: H10N 70/881 Switching materials
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 Complex metal oxides, e.g. perovskites, spinels

Abstract

Horizontally oriented and vertically stacked memory cells are described herein. One or more method embodiments include forming a vertical stack having a first insulator material, a first memory cell material on the first insulator material, a second insulator material on the first memory cell material, a second memory cell material on the second insulator material, and a third insulator material on the second memory cell material, forming an electrode adjacent a first side of the first memory cell material and a first side of the second memory cell material, and forming an electrode adjacent a second side of the first memory cell material and a second side of the second memory cell material.

Claims

1. A memory cell, comprising:

a memory cell material having a recess formed therein; and

an electrode conformally deposited in the recess in the memory cell material;

wherein the memory cell material is a self-aligned memory cell material.

2. The memory cell of claim 1, wherein the electrode is conformally deposited in the recess adjacent a side of the memory cell material.

3. The memory cell of claim 2, wherein the memory cell includes an additional electrode adjacent an additional side of the memory cell material.

4. The memory cell of claim 1, wherein the memory cell includes an insulator material on which the memory cell material is formed.

5. The memory cell of claim 4, wherein the memory cell includes an additional insulator material formed on the memory cell material.

6. The memory cell of claim 1, wherein the electrode comprises a portion of a data line.

7. A method of processing a memory cell, comprising:

forming a recess in a memory cell material, wherein forming the recess in the memory cell material includes removing a portion of the memory cell material; and

conformally forming an electrode in the recess in the memory cell material.

8. The method of claim 7, wherein conformally forming the electrode in the recess in the memory cell material includes conformally depositing the electrode in the recess in the memory cell material.

9. The method of claim 7, wherein the method includes removing the portion of the memory cell material using a selective wet etch.

10. The method of claim 7, wherein conformally depositing the electrode in the recess in the memory cell material includes conformally depositing the electrode in the recess in direct contact with a side of the memory cell material.

11. The method of claim 7, wherein conformally depositing the electrode in the recess in the memory cell material includes conformally depositing a metal material in the recess.

12. The method of claim 7, wherein the method includes removing a portion of the conformally deposited electrode.

13. The method of claim 7, wherein the method includes conformally forming the electrode in the recess in the memory cell material such that the electrode completely fills the recess.

14. A memory device, comprising:

a number of memory cells, wherein each of the number of memory cells includes;

a memory cell material having a recess formed therein; and

an electrode conformally deposited in the recess in the memory cell material; and

wherein the number of memory cells are self-aligned memory cells.

15. The memory device of claim 14, wherein the number of memory cells are vertically stacked memory cells.

16. The memory device of claim 14, wherein the number of memory cells are horizontally oriented memory cells.

17. The memory device of claim 14, wherein the number of memory cells include at least two memory cells.

18. The memory device of claim 14, wherein the number of memory cells comprise at least two vertical stacks of memory cells.