Graded dielectric structures

• US 9,627,501 B2
• Filed: 01/28/2015
• Issued: 04/18/2017
• Est. Priority Date: 08/30/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Gealy, F. Daniel, Bhat, Vishwanath, Srividya, Cancheepuram V., Rocklein, M. Noel
• Primary Examiner(s): Schoenholtz, Joseph
• Application Number:
  US14/607,733
• Publication Number:
  US 20150137254A1
• Time in Patent Office: 811 Days
• Field of Search: None
• CPC Class Codes: C23C 16/45529 specially adapted for making a layer stack of alternating different compositions or gradient compositions
• CPC Class Codes: H01L 21/02148 the material containing hafnium, e.g. HfSiOx or HfSiON
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/02189 the material containing zirconium, e.g. ZrO2
• CPC Class Codes: H01L 21/02194 the material containing more than one metal element
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/3141 Deposition using atomic layer deposition techniques [ALD]
• CPC Class Codes: H01L 21/3142 of nano-laminates, e.g. alternating layers of Al203-Hf02
• CPC Class Codes: H01L 21/31641 Deposition of Zirconium oxides, e.g. ZrO2
• CPC Class Codes: H01L 21/31645 Deposition of Hafnium oxides, e.g. HfO2
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 28/56 the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of electronic devices and systems. In an embodiment, a dielectric layer is graded with respect to a doping profile across the dielectric layer. In an embodiment, a dielectric layer is graded with respect to a crystalline structure profile across the dielectric layer. In an embodiment, a dielectric layer is formed by atomic layer deposition incorporating sequencing techniques to generate a doped dielectric material.

Claims

1. A device comprising:

a metal oxide doped with a dopant, the metal oxide having a top surface and a bottom surface, wherein the metal oxide has varying amounts of the dopant across the metal oxide between the top and bottom surfaces with concentrations of the dopant at the top surface and at the bottom surface each being greater than a concentration of the dopant in a center of the metal oxide between the top surface and the bottom surface, the dopant including a metal dopant and/or silicon.

2. The device of claim 1, wherein the metal oxide comprises monolayers across the metal oxide.

3. The device of claim 1, wherein the dopant includes a metal dopant.

4. The device of claim 1, further comprising first and second electrodes;

wherein the top and bottom surfaces are in contact with the first and second electrodes, respectively.

5. The device of claim 3, wherein the dopant concentration at the center of the metal oxide is less than a concentration of the metal dopant in any other part of the metal oxide.

6. The device of claim 1, wherein the metal oxide includes a binary metal oxide.

7. The device of claim 6, wherein the metal oxide includes any one of Lanthanide oxides, HfO2, ZrO2 and TiO2.

8. The device of claim 3, wherein the metal dopant includes more than one type of metal dopant.

9. The device of claim 4, wherein the metal oxide between the first and second electrodes is a dielectric layer of a capacitor.

10. A device comprising:

a metal oxide doped with a dopant, the metal oxide having a top surface and a bottom surface, wherein the metal oxide has varying amounts of the dopant across the metal oxide between the top and bottom surfaces with concentrations of the dopant at the top surface and at the bottom surface each being greater than a concentration of the dopant in a center of the metal oxide between the top surface and the bottom surface, wherein the center of the metal oxide includes a crystalline layer, and each of the first and second interfaces includes an amorphous layer.

11. A device comprising a capacitor, the capacitor including a dielectric layer between first and second electrodes, the dielectric layer including a metal oxide doped with a dopant, the metal oxide comprising:

a first interface region on a side of the first electrode, the first interface region having a first concentration of the dopant;

a second interface region on a side of the second electrode, the second interface region having a second concentration of the dopant; and

a intermediate region between the first and second interface regions, the intermediate region having a third concentration of the dopant, the third concentration being lower than each of the first and second concentrations, wherein the dopant includes a metal dopant and/or silicon.

12. The device of claim 11, wherein the metal oxide comprises monolayers across the metal oxide.

13. The device of claim 11, wherein the metal oxide includes a binary metal oxide.

14. The device of claim 13, wherein the metal oxide includes any one of Lanthanide oxides, HfO2, ZrO2 and TiO2.

15. The device of claim 11, wherein the dopant includes a metal dopant.

16. The device of claim 15, wherein the metal dopant includes more than one type of metal dopant.

17. A device comprising a capacitor, the capacitor including a dielectric layer between first and second electrodes, the dielectric layer including a metal oxide doped with a dopant, the metal oxide comprising:

a first interface region on a side of the first electrode, the first interface region having a first concentration of the dopant;

a second interface region on a side of the second electrode, the second interface region having a second concentration of the dopant; and

a intermediate region between the first and second interface regions, the intermediate region having a third concentration of the dopant, the third concentration being lower than each of the first and second concentrations, wherein the intermediate region of the metal oxide includes a crystalline layer, and each of the first and second interface regions includes an amorphous layer.

18. A device comprising a transistor, the transistor including a gate dielectric film having a first interface toward a gate electrode and a second interface toward a channel region, the gate dielectric film including a metal oxide doped with a dopant, wherein each of the first and second interfaces is larger in a concentration of the dopant than a center of the metal oxide between the first and second interfaces, the dopant including a metal dopant and/or silicon.

19. The device of claim 18, wherein the metal oxide includes a binary metal oxide.

20. The device of claim 18, wherein the dopant includes a metal dopant.